Threshold Logic Gate (TLG) is a potential alternative of Boolean Logic circuit. It is one of the fundamental components of neural network. An Optical Threshold Logic Gate (OTLG) has been designed in this paper, using a reflector telescopic system and a resonant Fabry-Perot cavity. Threshold logic gate consists of a weighted summing unit followed by a comparator. In the proposed OTLG, the weight of the input signal is varied using a polarizer-analyser combination. The threshold value, which is the reference of the comparator, is applied into the Fabry-Perot cavity with the help of a Beam splitter . AND, OR and NOT gates are implemented by setting the threshold values of the proposed OTLG.The system has been modelled analytically and studied using MATLAB and FINESSE. The simulation results for OTLG based Basic Gates are presented here.
A new implementation technique of 1-bit Full Adder using output wired CMOS inverter based threshold logic is presented. With the advancement of nano technology threshold gate based logic design has got a new direction. In this paper first carry output is designed using output wired CMOS inverter based majority gate. Then Sum output is designed using Threshold gate. The number of transistor is less than the CMOS based Full Adder Circuit. The major advantage of this CMOS Threshold gate is it's simplicity. It's delay time is only around three inverter delays. The proposed design has been verified by means of simulation using PSPICE.
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