Design of package BGA pin-out for >25Gb/s high speed SerDes considering PCB via crosstalk

Abstract

Fast growing bandwidth demands for networking and data center applications continuously face difficult signal integrity challenges. Among them, serializer/deserializer (SerDes) package pin-out and its corresponding printed circuit board (PCB) via crosstalk have become a significant source of high jitter and limit the performance of high speed serial links. In this paper, a variety of far-end crosstalk (FEXT) and nearend crosstalk (NEXT) SerDes pin-out patterns are designed and investigated to explore the crosstalk performance for interfaces running 25Gb/s and beyond. The impact of PCB routing layer selection and via stub are also considered. Both frequency domain and time domain analysis are studied based on 3-dimensional (3D) full wave electromagnetic (EM) simulation, and the results are compared along with the calculated integrated crosstalk noise (ICN) to find the pattern with better signal isolation. A PCB test vehicle is designed and manufactured to provide measurement and verification results by using broadband micro-probes and multi-port vector network analyzer (VNA). The optimized pinout is then selected to evaluate the overall link performance based on the input/output buffer information specification algorithmic modeling interface (IBIS-AMI) model from silicon vendors.

DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane

“…So, in the receiver a DFE with two parallel feedback paths combing with a PAM4 decoder is employed to cancel the post-cursor inter-symbol interference (ISI). In addition, for emulating actual link performance, impairments such as device package (pkg) and crosstalk are necessarily added into the link system in a form of S-parameter [12], [13]. Figure 2 gives a typical DFE for PAM4 system [14].…”