DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane

Abstract

This paper analyzes the effect of error propagation of decision feedback equalizer (DFE) for PAM4 based 400 Gb/s Ethernet. First, an analytic model for the error propagation is proposed to estimate the probability of different burst error length due to error propagation for PAM4 link system with multi-tap TX FFE (Feed Forward Equalizer) + RX DFE architecture. After calculating the symbol error rate (SER) and bit error rate (BER) based on the probability model, the theoretical analysis about the impact of different equalizer configurations on BER is compared with the simulation results, and then BER performance with FEC (Forward Error Correction) is analyzed to evaluate the effect of DFE error propagation on PAM4 link. Finally, two FEC interleaving schemes, symbol and bit interleaving, are employed in order to reduce BER further and then the theoretical analysis and the simulation result of their performance improvement are also evaluated. Simulation results show that at most 0.52 dB interleaving gain can be achieved compared with non-interleaving scheme just at a little cost in storing memory and latency. And between the two interleaving methods, symbol interleaving performs better compared with the other one from the view of tradeoff between the interleaving gain and the cost and can be applied for 400 Gb/s Ethernet.

41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

“…Moreover, there are some mathematical operations, such as convolution and Fourier transform, in the signal transmission process. Through simulation, it can be obtained that, compared with the non-interleaving scheme in reference [15], PBM can achieve an interleaving gain of 0.35 dB at the BER of 10 −7 , as shown in Figure 9a. This shows that PBM can reduce more error symbols caused by the same burst errors than FOM, but fewer than PSM.…”

“…Then, these interleaved data are aggregated through the multiplexer to further discrete errors and double the transmission rate. We have provided and theoretically explored the use of FEC Orthogonal bit Multiplexing (FOM), symbol Pre-interleaving Bit MUX (PBM) and symbol Pre-interleaving Symbol MUX (PSM) in detail [15]. The error-mitigation processes of non-interleaving and PBM are shown in Figure 7a,b, respectively.…”

“…This requires some optimization technologies at the circuit level. Further, focusing on the memory capacity for buffer codewords, MUX and the latency of interleaving, a performance comparison of these three FEC interleaving schemes is given in Table 1 [15]. In order to prepare all 16 symbols well before they are sent to MUX, PBM needs a 1500-bit memory, which consists of 150 bit, 300 bit, 450 bit and 600 bit to buffer 16 symbols from the first FEC lane to the fourth one, respectively.…”

“…To achieve our objectives, we propose and implement a high-speed high-depth preinterleaver of symbol pre-interleave bit muxing (PBM) to mitigate DFE error propagation. The theoretical level focuses on developing a cumulative probability distribution model to theoretically analyze the error probability and interleaving gain of PBM [15]. Due to the compensate constraint, the model is subject to a limit to the SerDes configuration with DFE.…”