Impact of System-in-Package in side-by-side discrete SoC-DRAM configurations on SI, PI and thermal performance

This paper proposes a system-in-package combination navigation chip. We used wire bonding, chip stacking, surface mount, and other processes to integrate satellite navigation chips, inertial navigation chips, microprocessor chips, and separation devices. Finally, we realized the hardware requirements for combined navigation in a 20 mm × 20 mm chip. Further, we performed a multi-physics simulation analysis of the package design. For antenna signals, the insertion loss was greater than −1 dB@1 GHz and the return loss was less than −10 dB@1 GHz. The amplitude of these noises of the signal between the MCU and the IMU was approximately 20%, and the maximum value of the coupling coefficient between signal lines on the top surface was 13.4174%. The ninth mode of the power plane yielded a maximum voltage of 55 mV, and all power delivery networks had a DC voltage drop of less than 2%. The highest temperature in the microsystem was approximately 42 °C. These results show that our design performed well in terms of signal, power, and thermal performance.

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Impact of System-in-Package in side-by-side discrete SoC-DRAM configurations on SI, PI and thermal performance

Cited by 2 publications

References 8 publications

A Modeling and Computational Analysis Method for Multichip DDR Microsystem

A Modeling and Computational Analysis Method for Multichip DDR Microsystem

Design and Simulation of a System-in-Package Chip for Combined Navigation

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