Design of Low-power Baseband-processor for RFID Tag

He, Yan; Jianyun, Hu; Li, Qiang; Min, Hao

doi:10.1109/saint-w.2006.15

Cited by 22 publications

(2 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2 shows the architecture of the passive RFID chip architecture. The RFID chip consists of RF power reception unit, a microprocessor and EEPROM [3]. The EEPROM contain the data of the tag.…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of Modeling Frequency Coded Serial Communication for Eurobalise Using ASK Module

Ehkan

Zakaria

Razalli

et al. 2014

AMM

View full text Add to dashboard Cite

This paper discusses about the modeling of frequency coded serial communication for the application of Eurobalise on hardware-based field programmable gate array (FPGA). The transceiver consists of FPGA and the ultra-high frequency (UHF) band amplitude shift keying (ASK) module. In the convention interface of the ASK transceiver module with the digital controller, noise has introduce into the channel. The noise in the output of ASK receiver has distorted the transmitted data causing the throughput of the wireless channel to be decreased. When the ASK module interfaces with the FPGA device, the noise from the output of the ASK receiver causing the receiving FPGA retarded. The purpose of the frequency coded serial data is to provide continuous specific frequency pulse train to the ASK transmitter. The original serial bit stream is then modulated in the pulse train with different frequency corresponding to the bit’s logic level. This technique has made the output of the ASK receiver to produce a very clean signal with extremely less noise. Hence, the receiver’s FPGA able to capture all the transmitted data accurately across traditional disciplinary boundaries, including computer hardware, algorithms, electronics interfacing and application domain.

show abstract

“…2 shows the architecture of the passive RFID chip architecture. The RFID chip consists of RF power reception unit, a microprocessor and EEPROM [3]. The EEPROM contain the data of the tag.…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of Modeling Frequency Coded Serial Communication for Eurobalise Using ASK Module

Ehkan

Zakaria

Razalli

et al. 2014

AMM

View full text Add to dashboard Cite

show abstract

“…During the communication between a tag and an interrogator, the tag is passive, meaning that it receives all its operating energy from the interrogator's RF waveform [2] . So it is important that an UHF RFID system works at ultra-low power in addition to the requirements of long operating range, high data rate, and low cost [3] .…”

Section: Introductionmentioning

confidence: 99%

Design of an ultra-low-power digital processor for passive UHF RFID tags

Wanggen

Zhang

et al. 2009

J. Semicond.

View full text Add to dashboard Cite

A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 µm process of Chartered Semiconductor.

show abstract