Design of High-Speed CAVLC Decoder Architecture for H.264/AVC

Abstract

In this paper, we propose hardware architecture for a high‐speed context‐adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920×1088 30 fps video in real time at a 30.8 MHz clock.

Context Adaptive Variable Length Decoding Optimization and Implementation on Tms320c64 Dsp for H.264/Avc

“…In literature, many other works focused on the algorithmic approaches that optimized methods to decode one or several syntax elements, such as [6], [7], [8] and [9]. In [6], new look up tables are introduced to decode TotalCoeff and TrailingOnes in one codeword of 19 bits instead of 16 bits. The Cofftoken step determines also the following skip steps, if they exist, to reduce the number of decoding steps.…”

“…The Cofftoken step determines also the following skip steps, if they exist, to reduce the number of decoding steps. In addition the design of [6] reduced the number of cycles for computing the codeword length of the current decoding block. This parameter is used to determine the next input bitstream (valid bits).…”

A low power multisymbol CAVLC decoder for H.264/AVC

“…2 shows the proposed CAVLC decoder architecture which is mainly composed of a coeff_token decoder, a level decoder, a total_zeros decoder, a run_before decoder, a barrel shifter, a control unit and an output buffer. In our design, an accumulator and two registers are removed from the previous architecture 5 to reduce the hardware overhead and save the power consumption.…”

A Novel Reconfigurable Processor Using Dynamically Partitioned SIMD for Multimedia Applications

“…In addition, the higher performance in video compression and decompression is required, the more complex hardware is needed as in [1]. Various hardware implementation methods for H.264 have been proposed [2]- [6]. Some partial or full H.264 encoders or decoders in [2]- [4] were developed by using an application-specific integrated circuit (ASIC) design method.…”

“…Various hardware implementation methods for H.264 have been proposed [2]- [6]. Some partial or full H.264 encoders or decoders in [2]- [4] were developed by using an application-specific integrated circuit (ASIC) design method. Although these encoders or decoders implemented by ASIC are very good for high performance, they have limitations in flexibility when some modifications are needed.…”