A Novel Reconfigurable Processor Using Dynamically Partitioned SIMD for Multimedia Applications

Lyuh, Chun‐Gi; Suk, Jung-Hee; Chun, Ik-Jae; Roh, Tae Moon

doi:10.4218/etrij.09.1209.0021

Cited by 8 publications

(4 citation statements)

References 8 publications

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“…Application-specific and reconfigurable single-instruction, multiple data (SIMD) processors are emerging as a low-cost alternative to general-purpose multi-core systems [2] [3]. In this paper, we investigate strategies for improving the yield of application-specific SIMT processors [1].…”

Section: Related Workmentioning

confidence: 99%

Yield-aware Performance-Cost Characterization for Multi-Core SIMT

Mozafari

Meyer

Skadron

2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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Redundancy is now routinely allocated in circuits, microarchitectural structures, or at the system level, to mitigate mounting manufacturing yield losses. In this paper, we propose spare lane sharing, which reduces the cost of multi-core SIMT systems by allowing one of two neighboring cores to make use of a redundant lane if necessary. We have evaluated the performance-cost trade-offs of core-, lane-, and shared-lane-sparing under a variety of benchmarks, and found that for nearly all applications shared-lane-sparing outperforms lane-sparing, reducing cost by up to 20%.

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Section: Related Workmentioning

confidence: 99%

Yield-aware Performance-Cost Characterization for Multi-Core SIMT

Mozafari

Meyer

Skadron

2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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“…Many CGRAs have been proposed in recent years [7]- [14]. The previous review [7] only summarizes some of the important CGRAs that were proposed before 2001.…”

Section: Related Workmentioning

confidence: 99%

“…ERP [14] is a novel reconfigurable processor that uses a dynamically partitioned single-instruction multiple-data (DP-SIMD) model. The control unit manages the external I/O and the internal PU array via a PUA configuration and data memory.…”

Section: Related Workmentioning

confidence: 99%

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

Gu-gang

Cao

Yang

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYOne of the largest challenges for coarse-grained reconfigurable arrays (CGRAs) is how to efficiently map applications. The key issues for mapping are (1) how to reduce the memory bandwidth, (2) how to exploit parallelism in algorithms and (3) how to achieve load balancing and take full advantage of the hardware potential. In this paper, we propose a novel parallelism scheme, called 'Hybrid partitioning', for mapping a H.264 high definition (HD) decoder onto REMUS-II, a CGRA systemon-chip (SoC). Combining good features of data partitioning and task partitioning, our methodology mainly consists of three levels from top to bottom: (1) hybrid task pipeline based on slice and macroblock (MB) level; (2) MB row-level data parallelism; (3) sub-MB level parallelism method. Further, on the sub-MB level, we propose a few mapping strategies such as hybrid variable block size motion compensation (Hybrid VBSMC) for MC, 2D-wave for intra 4 × 4, parallel processing order for deblocking. With our mapping strategies, we improved the algorithm's performance on REMUS-II. For example, with a luma 16 × 16 MB, the Hybrid VBSMC achieves 4 times greater performance than VBSMC and 2.2 times greater performance than fixed 4 × 4 partition approach. Finally, we achieve 1080p@33fps H.264 high-profile (HiP)@level 4.1 decoding when the working frequency of REMUS-II is 200 MHz. Compared with typical hardware platforms, we can achieve better performance, area, and flexibility. For example, our performance achieves approximately 175% improvement than that of a commercial CGRA processor XPP-III while only using 70% of its area.

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“…Other researchers focus on improving specific applications/algorithms, such as [26], [28], and [29], where a reconfigurable system is created to optimize a specific type of applications. Those researchers have shown the performance benefits for such reconfigurable SIMD/MIMD systems in the presence of parallelism diversity.…”

Section: Concept and Backgroundmentioning

confidence: 99%

Maximizing Energy Efficiency through Vertically Integrated Dynamic Reconfigurability

Arrabi¹

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Power and energy consumption have become some of the main hurdles for performance advancement in modern digital systems. High transistor densities and clock speeds have created significant thermal and power delivery issues, and increasingly pervasive portable electronic devices have limited energy sources but high performance expectations. Power affects and is affected by almost every aspect of digital system design, enticing designers and researchers to approach this problem from every possible aspect.This work explores two such aspects: dynamic reconfigurability and vertical integration. Dynamic reconfigurability is the ability to change the configuration of the system dynamically during runtime, and vertical integration is using low-level design information in high-level decisions (and vice-versa) as well as co-optimizing multiple design levels simultaneously. Both of these concepts can be targeted to various system metrics; in this work, they are used to reduce the total energy consumption of the system with the goal of increasing system battery lifetime while still providing the necessary performance and functional capabilities.This work explores dynamic reconfigurability and vertical integration through the use of three practical systems. We go through the steps and analysis in designing these systems that will show the potential benefits of our methods. Through the steps of designing the systems, we show the impact of several significant aspects of vertically integrated dynamically configurable systems, thus providing a framework for identifying potential benefits of reconfigurability and co-optimization and for general guidelines of how to implement them on other systems. We also look at the granularity of configurability and the overhead that it incurs, as well as the circuit-level details and information that might affect and be affected by architectural or system-level decisions.The first system is a wireless body sensor node that consumes most of its energy wirelessly transmitting data. We investigate how adaptive software can compress the data before sending without sacrificing information using only the limited processing and memory resources that typically reside on body sensors. We go through the various aspects that affect our solution and the different design levels we have to take into account when applying the compression.The second example system is a custom digital signal-processing system utilizing Panoptic Dynamic Voltage Scaling (PDVS), in which we investigate adding fine-grained spatial and temporal granularities of voltage scaling to the processor. We use a vertically integrated approach to explore the trade-offs of the ability to switch the voltage of a single arithmetic component (spatial) for a single operation (temporal), as well as the different variables that need to be considered for scheduling such systems.The third system is a Field Programmable Core Array (FPCA), in which we investigate various methods for creating a configurable processor capable of switching betwee...

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A Novel Reconfigurable Processor Using Dynamically Partitioned SIMD for Multimedia Applications

Cited by 8 publications

References 8 publications

Yield-aware Performance-Cost Characterization for Multi-Core SIMT

Yield-aware Performance-Cost Characterization for Multi-Core SIMT

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

Maximizing Energy Efficiency through Vertically Integrated Dynamic Reconfigurability

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