A low power multisymbol structure of CAVLC decoder customised for H.264/AVC baseline profile is presented. The dependency property of CAVLC algorithm limits the usage of parallelism and pipelining techniques, but other techniques such as table partitioning and multisymbol are adopted to decrease power and increase throughput. A top-level CAVLC architecture is proposed first and then its subdecoders are designed and analysed. Finally, the proposed CAVLC decoder is implemented in 0.18 mm CMOS technology. The estimated area and power consumption are 14873 gates and 14.46 mW, respectively. The critical delay time is 5.59 ns when the decoder is operating at 167 MHz. The proposed low power multisymbol CAVLC decoder can be suitably applied in H.264/AVC decoding systems.
The deblocking filter (DBF) is a system bottleneck of the whole decoder in terms of processing cycles. Based on the study and analysis of the basic filtering order and previously presented filtering orders, we put forward a competitive filtering scheme to reduce the filtering cycles and improve the system throughput. Then, a highly parallel and pipelined deblocking filter architecture is proposed accordingly. Comparison of various DBF solutions shows that the system performance of our proposal significantly outperforms the previous designs from 3.7 to 8.3 times. Moreover, our architecture can easily support real-time deblocking of 60 fps HDTV video, and it can be suitably integrated into the H.264/AVC decoder.
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