Design of a new squaring function for the Viterbi algorithm

Eshraghi, A.; Fiez, T.S.; Winters, Kel; Fischer, Thomas R.

doi:10.1109/4.309906

Cited by 32 publications

(26 citation statements)

References 12 publications

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“…The implementation proposed by Eshraghi et al [3] is faster and more area efficient when compared with conventional exact and table lookup approaches. This paper describes, briefly, the approximate squaring function presented in [3]. It then introduces an improved technique for computing the approximate squaring function.…”

Section: Introductionmentioning

confidence: 99%

“…The approximation presented in [3] is efficient, keeping in mind that the Viterbi algorithm will compensate for any inaccuracies and additional noise. The implementation proposed by Eshraghi et al [3] is faster and more area efficient when compared with conventional exact and table lookup approaches. This paper describes, briefly, the approximate squaring function presented in [3].…”

Section: Introductionmentioning

confidence: 99%

“…A fundamental mathematical function in realizing the Viterbi algorithm is the squaring function. Recently, Eshraghi et al [3] proposed an algorithm for the squaring function. The approximation presented in [3] is efficient, keeping in mind that the Viterbi algorithm will compensate for any inaccuracies and additional noise.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, Eshraghi et al [3] proposed an algorithm for the squaring function. The approximation presented in [3] is efficient, keeping in mind that the Viterbi algorithm will compensate for any inaccuracies and additional noise. The implementation proposed by Eshraghi et al [3] is faster and more area efficient when compared with conventional exact and table lookup approaches.…”

Section: Introductionmentioning

confidence: 99%

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Combinational logic approach for implementing an improved approximate squaring function

Hiasat

Abdel-Aty-Zohdy

1999

IEEE J. Solid-State Circuits

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The Viterbi algorithm is a fundamental signalprocessing technique used in different communication systems. An improved, implemented, and tested approximate squaring function for the Viterbi algorithm is introduced in this paper. The implementation of this improved squaring function is based on combinational logic design. The performance of this new approach has been verified by implementing a 7-bit squaring function chip in a 2-m CMOS technology. The active integrated circuit area of the chip was 380 2 400 m 2 , and the delays through this area were 5.7 and 3.0 ns for rising and falling edges, respectively.Compared with the design introduced in [3], this approach reduces error associated with approximation, simplifies the complexity of realization, reduces the integrated circuit area by at least 40%, and increases the speed by about 100%.Index Terms-Implementation, squaring function, very-largescale integration (VLSI) combinational logic design, Viterbi algorithm.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Combinational logic approach for implementing an improved approximate squaring function

Hiasat

Abdel-Aty-Zohdy

1999

IEEE J. Solid-State Circuits

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“…General purpose digital signal processors (DSP's) as well as application specific designs can benefit from using specialized squaring units instead of general purpose two operand multipliers [2], [3], [4], [5]. With technology advancements and the trend of increasing interconnect overhead, the use of ROM tables to implement the squaring function becomes more attractive.…”

Section: Introductionmentioning

confidence: 99%

Combined unsigned and two's complement hybrid squarers

Walters

Schlessman

Schulte

2001

Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256)

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Designs for high-speed combined squarers, capable of operating o n either unsigned or two's complement numbers, are presented. High speed is achieved in part by using a modestly sized ROM table to generate the less significant bits of the square, and wmbinational logic to generate the more significant bits. These squarers have a shorter carry propagate chain in the final adder and a smaller amount of combinational logic than previous hybrid designs. Area and delay estimates indicate that the combined hybrid squarers presented in this paper have between 28% and 64% percent less area and between 9% and 15% percent less delay than previous unsigned hybrid squarers f o r 32-bit operands.

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