A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.
Digital sections in several high-precision mixed systems operate at a relatively low frequency, allowing the trading of speed for the mitigation of switching noise and power distribution problems. While the serial clock distribution potentially solves most of these problems, the standard library cells and synthesis tools do not provide much, if any support for the serial clock tree implementation. In our work we propose the necessary design flow modification and seek the optimal clock signal allocation for the deployment of shadowed registers subject to timing constraints and minimal area overhead.
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