Combined unsigned and two's complement hybrid squarers

Abstract

Designs for high-speed combined squarers, capable of operating o n either unsigned or two's complement numbers, are presented. High speed is achieved in part by using a modestly sized ROM table to generate the less significant bits of the square, and wmbinational logic to generate the more significant bits. These squarers have a shorter carry propagate chain in the final adder and a smaller amount of combinational logic than previous hybrid designs. Area and delay estimates indicate that the combined hybrid squarers presented in this paper have between 28% and 64% percent less area and between 9% and 15% percent less delay than previous unsigned hybrid squarers f o r 32-bit operands.

Partial product reduction based on look-up tables

“…Nowadays, in the VLSI operator design, there are not many designs of hybrid combinationalstored logic operators [26]. LUTs are normally used to generate initial values or seeds; then, the execution of the algorithms is performed by combinational circuits [19], [21].…”

A Low Power High Performance Radix-4 Approximate Squaring Circuit

“…These designs primarily optimize by using hardwired bit product arrangements to reduce array sizes for efficient accumulation, mostly focusing on low precision. Since squaring is a unary operation, lookup tables have also been incorporated in proposed designs of squaring circuits [23,24]. Extension to the design of a radix-4 squaring circuit employing Booth recoding and "folding" of the partial products was introduced in [16], with further implementation optimization studies discussed in [10,11,17].…”

How to Square Floats Accurately and Efficiently on the ST231 Integer Processor

“…Recalling (7) and taking squares in (10), we obtain 2 (14). To establish the claimed upper bound we consider two cases:…”

“…For squaring in integer / fixed-point arithmetic several optimized hardware designs have been proposed; see for example [3, §4.9] as well as [14,4] and the references therein. However, for squaring in IEEE floating-point arithmetic much less seems to be available and to the best of our knowledge, no optimized design has been presented and analyzed in the details as we do here, be it in hardware or in software.…”