Design of a 3-D fully depleted SOI computational RAM

Abstract

We introduce a three-dimensional (3-D) processorin-memory integrated circuit design that provides progressively increasing processing power as the number of stacked dies increases, while incurring no extra design effort or mask sets. Innovative techniques for processor/memory redundancy and fast global bus evaluation are described. The architecture can be augmented with a nearest-neighbor physical 3-D communications network that can substantially reduce interconnect lengths and relieve routing congestion. The test chip, with 128 Kb of memory and 512 processing elements (PEs) on two fully depleted silicon-on-insulator (SOI) dies, can achieve a peak of 170 billion-bit-operations per second at 400 MHz.Index Terms-Memory architecture, multiprocessor interconnection, parallel processing, silicon-on-insulator (SOI) technology.

Effect of Wet Pretreatment on Interfacial Adhesion Energy of Cu-Cu Thermocompression Bond for 3D IC Packages

“…A schematic 3D IC structure 1,2 is shown in Fig. 1 where several chip-stacking methods are presented, such as the polymer thermocompression bond, 3 SiO 2 fusion bond, 4 Cu-solder-Cu bond, 5 and Cu-Cu thermocompression bond. 6 Of these techniques, the Cu-Cu thermocompression bond has the advantages of low electrical resistivity between the bonded surfaces, excellent resistance to electromigration, and prevention of brittle intermetallic compound formation.…”

3-D Topologies for Networks-on-Chip

“…The length of the crossbar switch also depends upon the number of router ports and the width of the buss (7) where and are the width and spacing or, alternatively, the pitch of the interconnect, respectively, and is the width of the communication channel in bits. Consequently, the worst case delay of the crossbar switch is determined by the longest path within the switch, which is equal to (7). The delay of the communication channel is (8) where and are the delay of the vertical and horizontal channels, respectively [see Fig.…”

3-D Topologies for Networks-on-Chip

“…The length of the crossbar switch also depends upon the number of router ports and the width of the buss 7where and are the width and spacing or, alternatively, the pitch of the interconnect, respectively, and is the width of the communication channel in bits. Consequently, the worst case delay of the crossbar switch is determined by the longest path within the switch, which is equal to (7). The delay of the communication channel is (8) where and are the delay of the vertical and horizontal channels, respectively [see Fig.…”