3-D Topologies for Networks-on-Chip

Abstract

Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3-D NoC are compared to that of 2-D NoC. Physical constraints, such as the maximum number of planes that can be vertically stacked and the asymmetry between the horizontal and vertical communication channels of the network, are included in speed and power consumption models of these novel 3-D structures. An analytic model for the zero-load latency of each network that considers the effects of the topology on the performance of a 3-D NoC is developed. Tradeoffs between the number of nodes utilized in the third dimension, which reduces the average number of hops traversed by a packet, and the number of physical planes used to integrate the functional blocks of the network, which decreases the length of the communication channel, is evaluated for both the latency and power consumption of a network. A performance improvement of 40% and 36% and a decrease of 62% and 58% in power consumption is demonstrated for 3-D NoC as compared to a traditional 2-D NoC topology for a network size of = 128 and = 256 nodes, respectively.

Proposing an optimal structure for the architecture of wireless networks on chip

“…Three-dimensional integration [14], optical interconnections [3] and WLs [6,7,10,11,15,16] are all methods for communicating between on-chip cores which aim to reduce latency and power consumption in NOC. Several studies have been conducted on the structure and routing algorithm related to ONoC.…”

Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router

“…Throughput is directly proportional to the number of directed edges and inversely proportional to the average distance of the network [27]. On the other hand, in a congestion free environment, latency is directly proportional to average distance of the network [28]. Thus, for any topology, the knowledge of the number of directed edges and the average distance are equally important as its diameter and bisection width.…”

“…Similarly for a generic M Â d(C/M)e mesh network with single core attached to each router (M is the number of nodes in each row and C is the total number of cores attached), the values of average distance (D) and number of directed edges (E) are given by [28],…”

A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms

“…Beyond traditional 2-D wired interconnect solutions, different revolutionary approaches were proposed. 3-D NoCs [28] make use of the advantages from both 3-D ICs and NoCs to improve latency, throughput and power consumption. Instead of employing express metal links, several on-chip interconnect alternatives have been proposed.…”