Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates

Abstract

In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99-126% and 121-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gats were 36 GHz and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.  Index Terms-Single flux quantum circuit, reconfigurable logic device, full adder.

30GHz Operation of Single-Flux-Quantum Arithmetic Logic Unit Implemented by Using Dynamically Reconfigurable Gates

“…⃝ 2016 The Institute of Electronics, Information and Communication Engineers configurable AND/OR gate [5]. The simulated normalized dc bias margin of the conventional dynamically reconfigurable AND/OR gate was 81-112% [10]. The bias margin was limited by the parasitic inductance of the signal merging parts.…”

“…The ALU has six arithmetic/logic functions: addition (ADD), two subtraction (SUB1 and SUB2), AND, OR, and exclusive-OR (XOR) in three pipeline stages. The ALU is composed of a bit-serial adder designed by using the dynamically reconfigurable AND/OR gate [10], two exclusive-OR (EXOR) gates, and five nondestructive read-out (NDRO) gates for reconfiguration of the circuit functions. We can select the functionality of the ALU by inputting six control signals (Set1-Set6) that set internal states of the NDROs.…”

“…The dynamically reconfigurable logic gates are suitable for high-speed reconfiguration of SFQ logic circuits compared to the other superconducting reconfigurable logic devices using phase shift elements [6], Manuscript [7], and can be applied to deep pipelined digital circuits [8], [9]. We have investigated circuit design methodology using dynamically reconfigurable SFQ logic gates [10]. Because the characteristics of the superconducting circuits are easily modulated by applying the magnetic field of a bias current, the design methodology can be applied not only to SFQ logic circuits but also to other superconducting circuits such as the quantum flux parametron [11], [12].…”

“…Because the characteristics of the superconducting circuits are easily modulated by applying the magnetic field of a bias current, the design methodology can be applied not only to SFQ logic circuits but also to other superconducting circuits such as the quantum flux parametron [11], [12]. The high-speed operation of the bit-serial adder designed by using dynamically reconfigurable SFQ logic gates has been demonstrated [10]. However, the measured operating margin of the bit serial adder was narrow because of the unstable operation of the dynamically reconfigurable SFQ AND/OR gate, the function of which is reconfigured to AND-and OR-modes by inputting control signals.…”

Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis

“…In this context, the reconfigurable logic gate (RLG) is one of the promising candidates as it may improve logic circuit area efficiency by increasing the number of functions performed by a fixed number of gates. To achieve this goal, researchers have developed operator-rich RLGs using emerging device technologies, such as quantum, optical, spintronic, ferroelectric, semiconductor, ReRAM, nanotube, and silicon nanowire devices [4][5][6][7][8][9][10][11][12][13][14][15][16][17]. These RLGs can switch between two or more operators with a small overhead in area and performance.…”