Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis

Abstract

In this paper, we propose a generic design methodology to achieve area-efficient reconfigurable logic circuits by using exact synthesis based on Boolean satisfiability (SAT) solver. The proposed methodology better leverages the high representation ability of emerging reconfigurable logic gates (RLGs) to achieve reconfigurable circuits with fewer gates. In addition, we propose a fence-based acceleration method to provide >10× speed up for the synthesis without an observable loss of optimality. Furthermore, four sets of RLGs are developed based on a recently proposed valley-spin device as a case study to demonstrate the advantage of the proposed circuit. Simulations have been performed to analyze the impact of the fence searching algorithm and combination of operators. Based on disjointsupport decomposable (DSD) benchmarks, up to 38% and 73% reductions are observed in the area and energy-delay-area product (EDAP), respectively, compared to CMOS counterparts. Compared to the two existing synthesis methods, the proposed scheme provides 40% and 26.3% reduction in EDAP based on MCNC benchmark.

Directed Acyclic Graph-Based Datapath Synthesis Using Graph Isomorphism and Gate Reconfiguration

“…With a slightly increased overhead, refs. [29,39] provides logic gate modules that reconfigure between arbitrary two-input Boolean functions by manipulating the Valley Pseudospin degree of freedom. Figure 1c demonstrates a brief example of how reconfigurable gates can simplify circuits.…”

“…If the inverter is not connected to a reconfigurable gate, we transform the conventional gate driven by the inverter into a reconfigurable gate that dynamically switches the input complementation status based on the control signal. This approach offers area advantages compared to inserting an XOR gate, especially considering that input/output negation is at a lower area cost in certain technologies, such as Valley Spin devices [29]. However, if the inverter drives multiple gates, merging the inverter/wire with the driven gates may not be area-efficient.…”

“…In addition to simply leveraging reconfigurable logic gates as compact logic models within libraries, several methodologies have been proposed to uncover circuit-level resource sharing through gate-level reconfiguration. For instance, [29] introduces a satisfiable SAT-based exact synthesizer that utilizes reconfigurable logic gates to realize two arbitrary functions within a single network. While this approach is area-optimal, it is primarily applicable to small-scale circuits.…”

“…For instance, ref. [29] introduces a satisfiable SAT-based exact synthesizer that utilizes reconfigurable logic gates to realize two arbitrary functions within a single network. While this approach is area-optimal, it is primarily applicable to small-scale circuits.…”