Design Challenges and Solutions for Ultra-High-Density Monolithic 3D ICs

Abstract

Monolithic three-dimensional integrated chips (3D ICs) are an emerging technology that offers an integration density that is some orders of magnitude higher than the conventional through-silicon-via (TSV)-based 3D ICs. This is due to a sequential integration process that enables extremely small monolithic inter-tier vias (MIVs). For a monolithic 3D memory, we first explore the static random-access memory (SRAM) design. Next, for digital logic, we explore several design styles. The first is transistor-level, which is a design style unique to monolithic 3D ICs that are enabled by the ultra-high-density of MIVs. We also explore gate-level and block-level design styles, which are available for TSV-based 3D ICs. For each of these design styles, we present techniques to obtain the graphic database system (GDS) layouts, and perform a signoff-quality performance and power analysis. We also discuss various challenges facing monolithic 3D ICs, such as achieving 50% footprint reduction over two-dimensional (2D) ICs, routing congestion, power delivery network design, and thermal issues. Finally, we present design techniques to overcome these challenges.

Centeral Electric Field and Threshold Voltage in Accumulation Mode Junctionless Cylindrical Surrounding Gate MOSFET

“…Figure 2 shows the transfer characteristic curves obtained using Equation (1). As can be seen in Figure 2, Equation (1) agrees well with the two-dimensional simulation value, so we will use Equation (1) in this paper.…”

“…Multi-gate MOSFETs are being developed with three dimensional design technology [1], [2] as a three-dimensional structure that reduces the short channel effects that occur in conventional CMOSFETs. The most successful device is FinFET.…”

Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

“…M3DICs are designed with a transistor, a logic gate, and system blocks, which are integrated vertically to equip the M3DIC in accomplishing higher integration than a 2D conventional circuit. In ICs, each block is connected using a vertical interconnect that can be shorter than a horizontal interconnect and can achieve a lower critical delay [ 5 , 6 , 7 , 8 , 9 , 10 , 11 ]. Each vertically stacked block has an electrical coupling between the upper and lower tiers.…”

Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology

“…Parallel integration only adds connectivity using TSVs, which are unlikely to result in significant improvement due to the large TSV pitches and sizes [1]- [2]. As for the state-of-art monolithic 3D integration, transistor-level monolithic 3D IC has the most fine-grained vertical connections to date thanks to the small monolithic inter-tier vias (MIVs) in cells, while still uses conventional CMOS interconnections for inter-cell connections despite the shrinking cell footprints, which leads to various issues including pin and routing congestions [5]. Specifically, in transistor-level monolithic 3D, routing congestion is caused by reduced pin access on the input/output metal port of each standard cell.…”

“…While a typical 14nm FinFET based 2D cell has at least 6 pin access points, a 3D cell may have only 3-4 due to its reduced footprint and the area occupied by MIVs. Gatelevel monolithic 3D IC has even less fine-grained vertical connections than transistor-level 3D IC [5].…”