Design-based metrology: advanced automation for CD-SEM recipe generation

Abstract

The procedure for properly implementing OPC for a new technology node or chip design involves multiple steps: selection of the RET (resolution enhance technique), selection of design rules, OPC Model Building, OPC Verification, CD control quantification (across chip, reticle, wafer, focus, exposure, etc) , calibration of Optical Rule Checks (ORC), and other verification steps. Many of these steps require up to thousands of wafer measurements, and while state-of-the-art CD-SEM tools provide automated metrology for production, manually creating a CD recipe with thousands of unique sites is extremely tedious and error-prone. This places a practical limit on both the quality and number of measurements that can be acquired during the technology development and qualification period. At the same time, the number of measurements required to qualify a new reticle design has increased drastically due to the growing complexity of RET and diminishing tolerances.To meet this challenge, a direct and automated link from the design systems to the process metrology tools is needed. Novel methodologies must also be developed to enable automated generation of the recipe from the design inputs and to translate the flood of metrology results into information that can improve the design, mask data processing, or the patterning process. To facilitate this two-way data flow, a new framework has been created enabling true Design-Based Metrology (DBM), and an application named OPC-Check has been developed to operate within this framework. This DBM framework provides the common language and interface that facilitates the direct transfer of desired measurement locations from the design to the metrology tool. This link is a critical element in Design for Manufacturability (DFM) efforts, a central theme in many presentations at Microlithography 2005. This article discusses the significant benefits of the tight integration of design and process metrology for OPC implementation in a new technology node, and provides some examples of the novel OPC-Check application as currently implemented at AMD SDC with Applied Materials CD-SEM tools.Below lOOnm, shrinking device geometries have placed tremendous pressure on optical lithography and mask technologies to effectively manage the patterning process, even with significant increases in numerical aperture (NA) and decreases in wavelength. This loss of resolving power, seen as diminished pattern printing capability on the wafer, has forced the semiconductor industry to use more aggressive scanner illumination strategies such as annular, quasar, and now dipole illumination conditions (ref I. Matthew, C. Tabery SPIE2005 ). In addition, multiple process layers are also using phase shift masks to maintain resolution as critical features shrink in size.

Automatic CD-SEM offline recipe creation in a high volume production fab

“…AMD has a metrology request application (MRA) in place [2,3] which compiles the required information for a given site list from various databases in a user-friendly way and directly yields the full data package which is needed as input for, e.g., the OPC Check application. All offline recipes evaluated in this work were created based on the AMD MRA system.…”

Design-driven metrology: a new paradigm for DFM-enabled process characterization and control: extensibility and limitations

“…This second figure of merit (recipe generation time), which might vary from less than a hour to few hours depending on the number of sites, wafer processing conditions and geometrical characteristics of the patterned shapes is less critical than PRA success-rate, as long as recipe generation can be performed on a MTI computer hardware independent of the SEM tool. Detailed state-of-the art results can be found in the technical literature 6,7 . Selection of the optimal area for automated focus setup (autofocus) is another critical component of a MTI.…”

DFM flow by using combination between design based metrology system and model based verification at sub-50nm memory device

“…Formerly, developers of design-based metrology are focused on automatic recipe generation, validation of OPC and RET within wafer and so forth. [3] Because the growing complexity of RET/OPC and diminishing tolerances, inner chip variation should be emphasized to get accurate prediction on whole design. New DBM system would be able to address this problem by measuring whole chip CD variation and statistical information.…”