Design-driven metrology: a new paradigm for DFM-enabled process characterization and control: extensibility and limitations

Capodieci, Luigi

doi:10.1117/12.659181

Cited by 5 publications

(2 citation statements)

References 10 publications

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“…The metrology algorithm within the CD-SEM metrology is one example of setup parameters that need to be defined accurately for each measurement location [1,2]. Correct choice of the metrology algorithm is critical for proper identification of the feature profile, leading to more accurate creation of simulation models and measurement of exposure dose and focus.…”

Section: Introductionmentioning

confidence: 99%

Automatic metrology algorithm identification using Pattern Matching

Fischer¹,

Akid²,

Abdelhaliem³

et al. 2015

2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

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the number of measurement points and their types are increasing with the increasing challenges of the new technology nodes. The industry is challenged to enhance and automate the current Design Based Metrology (DBM) recipe generation flow. This paper describes a novel methodology based on Pattern Matching (PM) to automate the flow of assigning the metrology algorithm parameter to each measurement location. Each measurement location in the design space is examined against a pre-populated database of patterns to select the proper metrology algorithm. The proposed technique increases the speed and efficiency of assigning this parameter to each location, and hence increases the speed of CD-SEM recipe generation. This novel flow is expected to ensure consistency between process characterization, modeling, verification and product monitoring and control.

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Section: Introductionmentioning

confidence: 99%

Automatic metrology algorithm identification using Pattern Matching

Fischer¹,

Akid²,

Abdelhaliem³

et al. 2015

2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

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“…[1], [2] A methodology to derive restrictive design rules has been described in this study. We perform through process window study of CD error for a range of patterns generated by layout DOE.…”

Section: Introductionmentioning

confidence: 99%

Application of layout DOE in RET flow

Zhang

Adrichem

et al. 2008

SPIE Proceedings

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At low k1 lithography and strong off-axis illumination, it is very hard to achieve edge-placement tolerances and 2-D image fidelity requirements for some layout configurations. Quite often these layouts are within simple design rules constraint for a given technology node. Evidently it is important to have these layouts included during early RET flow development. Simple shrinkage from previous technology node is quite common, although often not enough. For logic designs, it is hard to control design styles. Moreover for engineers in fabless design groups, it is difficult to assess the manufacturability of their layouts because of the lack of understanding of the litho process.Assist features (AF) are frequently placed according to pre-determined rules to improve lithography process window. These rules are usually derived from lithographic models. Direct validation of AF rules is required at development phase.To ensure good printability through process window, process aware optical proximity correction (OPC) recipes were developed. Generally rules based correction is performed before model based correction. Furthermore, there are also lots of other options and parameters in OPC recipes for an advanced technology, thus making it difficult to holistically optimize performance of recipe bearing all these variables in mind.In this paper we demonstrate the application of layout DOE in RET flow development. Layout pattern libraries are generated using the Synopsys Test Pattern Generator (STPG), which is embedded in a layout tool (ICWB). Assessment gauges are generated together with patterns for quick correction accuracy assessment. OPC verification through full process is also deployed. Several groups of test pattern libraries for different applications are developed, ranging from simple 1D pattern for process capability study and settings of process aware parameters to a full set of patterns for the assessment of rules based correction, line end and corner interaction, active and poly interaction, and critical patterns for contact coverage, etc.Restrictive design rules (RDR) are commonly deployed to eliminate problematic layouts. We demonstrate RDR evaluation and validation using our layout design of experiments (DOE) approach. This technique of layout DOE also offers a simple and yet effective way to verify AF placement rules. For a given nominal layout features all possible assist features are generated within the mask rules constraint using STPG. Then we run OPC correction and assess main feature critical dimension (CD) at best and worst process condition in ICWB. Best assist feature placement rules are derived based on minimum CD difference. The rules derived from this approach are not the same as those derived from the commonly used method of least intensity variation.

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