Design and use of memory-specific test structures to ensure SRAM yield and manufacturability

Abstract

High-density and high-performance single-port and dual-port SRAM increasingly occupy a majority of the chip area in

Breaking the simulation barrier: SRAM evaluation through norm minimization

“…Therefore, a priori it is hard to meet the requirement of one-in-million cell failure rate while being economically viable -poor prediction can lead to severe mis-estimation of yield. In the context of SRAM applications, typical interest is in maximizing the density of the cells, and thus minimizing their size, while maintaining an acceptable level of the failure probability [7]. However, as previously observed [10], the variations due to dopant fluctuations increase with the decrease in the gate area.…”

Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below

“…Only in recent years have the benefits of addressable yield characterization arrays made them economically compelling, 7 resulting in renewed interest in specialized BEOL characterization arrays. [8][9][10][11] They inherently isolate defects to a few microns in space, and to a specific level. They can also have significantly quicker test times than passive test circuits.…”