A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology

Wissel, L.; Pilo, H.; LeBlanc, Cathie; Wang, Xiaopeng; Lamphier, S.; Fragano, M.

doi:10.1109/cicc.2007.4405673

Cited by 7 publications

(2 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A high performance SRAM provides not only valuable yield information, but also performance information relevant to ultimate products [1]. For very large scale SRAM, the decoding time (from clock to wordline) and the data output time (from local sense amplifier to global I/O) in a read cycle are both transmitting long signals through long distance metal lines.…”

Section: Introductionmentioning

confidence: 99%

A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique

Zheng

Liu

Chen

et al. 2012

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

View full text Add to dashboard Cite

This paper focuses on high speed embedded SRAM design, especially on novel circuit technique to improve SRAM access time. A new two-stage sensing scheme which is able to reduce long interconnection metal line delay by transferring differential signals with half swing amplitude has been proposed. Post-layout simulation results show that the long distance signal transmission time has been decreased by 45%. Chip measurement shows the access time has been decreased by 23% at the expense of little area penalty (1.3%) and some read power penalty (about 16%) mainly caused by 2nd-stage sense amplifiers.

show abstract

Section: Introductionmentioning

confidence: 99%

A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique

Zheng

Liu

Chen

et al. 2012

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

View full text Add to dashboard Cite

show abstract

“…Address decoding is the first step for writing and reading operations that can occupy 50% of all the total time delay in large capacity SRAM [5]. Our address decoder of SRAM compiler using the secondary static decoder, its work contains two steps, the first step is pre-decoding, which may using the 1-to-2decoder, 2-to-4decoder and 3-to-8decoder, the second step is sec-decoding, it generates more signals from the pre-decoding signal by nand operations.…”

mentioning

confidence: 99%

Time Delay Model for SRAM Compiler

Song

Peng

Zhou

et al. 2013

AMM

View full text Add to dashboard Cite

In this paper, we introduced an effective time delay model for SRAM compiler, which represents an important performance of SRAM. Our method divide the delay time into several periods, including decoder delay, word line delay, bit line delay and SA delay. The theory is useful in predicting the delay time when the SRAM size is changed. Simulations by Hsim in 65nm CMOS process proves a high accuracy.

show abstract

A 65nm embedded low power SRAM compiler

Zheng

Gao

et al. 2010

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

View full text Add to dashboard Cite

A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology

Cited by 7 publications

References 3 publications

A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique

A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique

Time Delay Model for SRAM Compiler

A 65nm embedded low power SRAM compiler

Contact Info

Product

Resources

About