We have measured stress variations with temperature as a function of film thickness and a given grain size in pure Al and Al–0.5% Cu films on Si substrates. The variation in thickness for a given grain size is brought about by using the same film and the repeated controlled growth and dissolution of a barrier anodic oxide which can be grown uniformly on the film. Stress measurements were made as a function of temperature by measuring wafer curvature after successively removing each 0.1 μm of Al film. The components of strengthening due to the film thickness and the presence of grain boundaries were separated by assuming that the flow stress of the film is simply the sum of these two components. It is found that strengthening due to film thickness varies inversely with the thickness, which is consistent with results obtained by us using laser-reflowed films in an earlier work. The Hall–Petch coefficients calculated from the strengthening due to the grain boundaries are slightly higher than those reported for bulk Al. However, it is also recognized that the variation of the flow stress as g−1, where g is the grain size, is more plausible than that predicted by the Hall–Petch relation (i.e., as g−1/2). The variations of these two components with temperature, and under tension and compression, are discussed.
The adoption of permissioned blockchain networks in enterprise settings has seen an increase in growth over the past few years. While encouraging, this is leading to the emergence of new data, asset and process silos limiting the potential value these networks bring to the broader ecosystem. Mechanisms for enabling network interoperability help preserve the benefits of independent sovereign networks, while allowing for the transfer or sharing of data, assets and processes across network boundaries. However, a naive approach to interoperability based on traditional point-to-point integration is insufficient for preserving the underlying trust decentralized networks provide. In this paper, we lay the foundation for an approach to interoperability based on a communication protocol that derives trust from the underlying network consensus protocol. We present an architecture and a set of building blocks that can be adapted for use in a range of network implementations and demonstrate a proof-of-concept for trusted data-sharing between two independent trade finance and supply-chain networks, each running on Hyperledger Fabric. We show how existing blockchain deployments can be adapted for interoperation and discuss the security and extensibility of our architecture and mechanisms.
IntroductionA high performance 0.20pm logic technology has been developed with six levels of planarized copper interconnects. 0.15pm transistors (Lg,,,=0.15+0.04pm) are optimized for 1.8V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects. Critical layer pitches for the technology are summarized in Table 1 and enable fabrication of 7.6pm2 6T SRAM cells.Isolation and Transistors CMP planarized shallow trenches with good electrical isolation down to n+/p+ spacings of 0.5pm were fabricated (Fig. 1). Dual gate 0.15pm transistors with 35A physical gate oxides (accumulation t,,=39A measured at Vg=+l .SV) were formed using super steep retrograde channels, shallow extensions and halos, relatively deep source/drain regions and 1 OOnm nitride spacers. CoSi, was selectively formed on the polysilicon gates and source/drain regions with a nominal sheet resistance of 9Wsq. Rapid thermal processing was utilized as much as possible throughout the flow to minimize transient enhanced dopant diffusion.Fig. 2 shows a typical SEM cross-section of a NMOS transistor with a gate length of 0.15pm. Well delineated shallow S/D extensions and the deeper S/D junctions are clearly observed. The saturation drive currents for nominal gate length NMOS and PMOS devices are shown in Fig. 3 . The nominal drive currents are 630pNpm for NMOS and 230pA/ym for PMOS at 1.8V. The off-state leakage currents of these devices are well below the worst case leakage specification of 2nA/pm. The drain induced barrier lowering (DIBL) measured on NMOS and PMOS devices is plotted as a function of Leff in Fig. 4. Good short channel characteristics are maintained down to effective channel lengths of O.1ym. The Vt roll-off for N and P devices in the linear and saturation regions are shown in Fig. 5. The Vt's are 0.44V and -0.46V for Nch and Pch respectively, at a gate length of 0.15pm and the associated subthreshold slopes are less than 90mv/dec. The use of nitrided gate oxides was investigated due to their superior hot carrier reliability. Fig. 6 compares the degradation under hot carrier stress of nitrided oxides to thermal oxides and highlights the improved reliability of NO-annealed oxides. Peak Gms comparable to those from thermal oxides were obtained (Fig. 7). A further advantage afforded by nitrided gate dielectrics is its superior boron blocking properties, Increasing the poly silicon doping in the P+ gate to reduce poly depletion resulted in only a 88mV Vt shift in nitrided oxides (Fig. 8) compared to a 300mV Vt shift in thermal oxides. A significant reduction in the inversion to, is achieved with the higher gate doping, resulting in improved device characteristics. NMOS transistor design focused on minimizing defect enhanced dopant re-distribution such as TED. To this end, the effect of different source/drain implant energies on NMOS transistor performance is shown in Fig. 9. The lower energy implant results in a significantl...
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