Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below

A Survey of Yield Modeling and Yield Enhancement Methods

“…Instead, several papers have proposed array structures [48]- [51], designed like a memory array, as shown in Fig. 9.…”

A 65-nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array With Integrated Analysis Software

“…Briefly, addressable array circuits offer significantly higher area efficiency due to reduced probe pad count, reduced test time, and the ability to isolate fails to a few microns in space and to a specific level [4]. With only a small area of a reticle field used, the addressable array can be 0894-6507/$25.00 © 2008 IEEE repeated in the reticle field like a small product die, enabling visibility into across-die process variations.…”

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment

“…Recent developments of structured ASIC most center on mask programmability of logic circuits [2], [4], [10], [13], [15]. These addressing fast design derivations on a common platform allow frequent product feature changes and achieve reductions in both non-recurring engineering cost and time to market.…”