Design and implementation of a 16 by 16 low-power two's complement multiplier

Goldovsky, A.; Patel, Binta; Schulte, Michael; Kolagotla, R.K.; Srinivas, H.R.; Burns, G.

doi:10.1109/iscas.2000.857435

Cited by 23 publications

(9 citation statements)

References 15 publications

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“…To see why this is achievable, we observe that the outputs of the on-the-fly converter arrive at the multiplexer 11 unit delays earlier than the selection signal of the multiplexer. Based on this observation, the work in [6] proposed to use a strategic array of (3, 2), (5, 3), (7,4) compressors to enhance the operation speed of the part of the least significant product (LSP) terms.…”

Section: Conventional Left-to-right Full-width Multipliermentioning

confidence: 99%

“…Therefore, the speed-up design [6] focused on reducing the signal propagation delay of the LSP part. However, in the design of fixed-width left-to-right multipliers, most gates lying in the LSP part will be deleted.…”

Section: The Left-to-right Fixed-width Multiplier 31 Selection Of Thmentioning

confidence: 99%

“…Therefore, the previously described speed bottleneck from the LSP in the full-width multiplier disappears in this case. In other words, we can obtain a high-speed fixed-width multiplier just with an array structure, and we don't need any compressors in the LSP to accelerate the operating speed as proposed in [6].…”

Section: The Left-to-right Fixed-width Multiplier 31 Selection Of Thmentioning

confidence: 99%

“…Recently, the left-to-right algorithm without a final carry propagation step [4]- [5] had been proposed in an attempt to improve the performance of the right-to-left algorithm. More recently, the work [6] [7] used several kinds of compressors in the LSB parts of the partial product reduction array to further increase the operating speed of a left-to-right multiplier. However, to the best of our knowledge, no one fixed-or reduced-width multiplier adopts the left-to-right algorithm.…”

Section: Introductionmentioning

confidence: 99%

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Low-power fixed-width array multipliers

Wang

Kuo

Yang

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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A fixed-width multiplier using the left-to-right algorithm for partial-product reduction is presented. The high-speed feature offered by this design is used to trade for low power. In one design, the proposed multiplier not only owns 8% speed improvement but also gains 14% power and 13% area reduction. When applying the voltage scaling to balance the speed, the power reduction is increased to 29%.

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Section: Conventional Left-to-right Full-width Multipliermentioning

confidence: 99%

Section: The Left-to-right Fixed-width Multiplier 31 Selection Of Thmentioning

confidence: 99%

Section: The Left-to-right Fixed-width Multiplier 31 Selection Of Thmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low-power fixed-width array multipliers

Wang

Kuo

Yang

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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“…In [2], this LRCF approach was extended to produce 2n-bit product. It was also discovered that glitches in L-R reduction arrays were smaller than in the conventional R-L arrays, especially for data with large dynamic range [5,20,7].…”

Section: Introductionmentioning

confidence: 99%

High-performance left-to-right array multiplier design

Huang¹,

Ercegovac²

16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings.

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We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed design shows equivalent performance as tree multipliers for n ≤ 32. An efficient radix-4 recoding logic generates the partial products in a left-to-right order. The partial products are split into upper and lower groups. Each group is reduced using [3:2] adders with optimized signal flows and the carry-save results from two groups are combined using a [4:2] adder. The final product is obtained with a prefix adder optimized to match the non-uniform arrival profile of the inputs. Layout experiments indicate that upper/lower split multipliers have slightly less area and power than optimized tree multipliers while keeping the same delay for n ≤ 32.

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A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures

Oliveira

Santos

Ferrão

et al.

Vlsi-Soc: From Systems to Silicon

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This paper presents performance comparisons between two multipliers architectures. The first architecture consists of a pure array uses a radix-4 encoding to reduce the partial product lines. The second describe a design methodology to physically implement these architectures in with the pipelined Modified Booth. We compare the physical implementations in terms of area, power and delay. The results show that the new pipelined array multiplier can be significantly more efficient, with close to 16% power savings and 55% power savings when considering non-pipelined architectures. delay results. Up to now only results at the logic level were presented in WWW home page: http://www.inesc-id.pt multiplier that was modified to handle the sign bits in 2's complement and a pipelined and non-pipelined form, obtaining area, power consumption and architecture implemented was the widely used Modified Booth multiplier. We

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Design and implementation of a 16 by 16 low-power two's complement multiplier

Cited by 23 publications

References 15 publications

Low-power fixed-width array multipliers

Low-power fixed-width array multipliers

High-performance left-to-right array multiplier design

A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures

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