Design and analysis of FINFET pass transistor based XOR and XNOR circuits at 45 nm technology

Abstract

The conventional single-gate MOSFETs faces great challenges in scaling down of devices due to the severe shortchannel effects that reason an exponential gain in the leakage current. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits because of the self-alignment of the two gates. Design of XOR and XNOR circuits is suggested to improve the speed and power of these circuits and is basic building block of many arithmetic circuits. This paper compares and evaluates the performance of various designs of pass transistor based XOR and XNOR circuits. This paper demonstrates comparative performance study of high speed, low power and low voltage on XOR and XNOR digital circuit. The performances of XOR and XNOR circuits are based on CADANCE VIRTUOSO tool at 45 nm by applying voltage supply 0.7 voltages and the temperate is 27 0 C. Simulation results reveal low power, delay, power, delay product (PDP), average dynamic power consumption, energy delay product (EDP).

Leakage current reduction in finfet based 6T SRAM cell for minimizing power dissipation in nanoscale memories

“…Another circuit containing two series PMOS transistors connected in parallel with a NMOS transistor between 6T FinFET SRAM cell and GND. Both of these circuits are termed as USVL (upper SVL) and LSVL (lower SVL) respectively which together provides the reduced leakage to the FinFET based 6T SRAM cell [6][7][8].…”

Leakage and delay analysis in FinFET array multiplier circuits

“…Saraswat et al compared the performance of a full adder cell based on 45nm CMOS and FinFET technology, showing a decrease in both delay and power [10]. Yadav et al proposed FinFET pass transistor logic XOR and XNOR circuits and demonstrated they had good output signals while consuming less power and having comparable speed to CMOS versions [11].…”

“…Several digital designs have utilized FinFETs and exceeded the performance offered by similar size CMOS [10][11][12]. Agostinelli et al compared the leakage and delay between FinFETs and bulk CMOS for several logic circuits; it was shown that FinFETs had considerably less leakage at the cost of an increase in delay [6].…”

Power Analysis of an mRNA-Ribosome System

“…So, total power dissipation from a GTP hydrolysis can be obtained as follows. But even in the latest and best CMOS technology, FinFET technology, a XOR operation dissipates the power of 4.2 × 10 −8 J/s to perform XOR operation [13]. In FinFET technology, a shifter, such as a single bit shift register, being composed of single ip-op, also dissipates the power of 1.68 × 10 −7 joule in one second to perform the operation [13].…”

“…But even in the latest and best CMOS technology, FinFET technology, a XOR operation dissipates the power of 4.2 × 10 −8 J/s to perform XOR operation [13]. In FinFET technology, a shifter, such as a single bit shift register, being composed of single ip-op, also dissipates the power of 1.68 × 10 −7 joule in one second to perform the operation [13]. Table 1 provides a comparative view of power requirements for the discussed important operations on a conventional machine and on an mRNA-Ribosome system.…”