The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as multipliers. The characterization and optimization of such low power multipliers will aid in comparison and choice of multiplier modules in system design. In this paper we performed a comparative analysis of the power, delay, and power delay product (PDP) optimization characteristics of four parallel digital multipliers implemented using low power 10 transistor (10T) adders and conventional CMOS adder cells. In order to achieve optimal power savings at smaller geometry sizes, we proposed a heuristic approach known as hybrid adder models. Multipliers realized using the Static Energy Recovery Full adder (SERF) circuit consumed considerably less power compared to 10T and static CMOS based multipliers for all the configurations studied. Furthermore, the difference between the power consumption of the 10 transistor based multipliers and 28T multipliers is significant at 180 nm, but not at 70 nm. For smaller geometry sizes down to 70 nm, the propagation delay of the multipliers implemented with 10 transistors translates to a better performance measure. Carry-Save Multipliers had better PDP range than the other multipliers for all the three adder sub-module designs. The PDP measure for optimal scaled gate width resulted in a best-case scenario for SERF Wallace tree multiplier as compared to the other three SERF based multipliers. This can be attributed to the fast computational capability of the Wallace Tree multiplier and SERF adders' recovery energy logic saving more power at deep sub-micron sizes. The proposed SERF-10T Hybrid adder model multipliers consumed the least power of all the Hybrid and regular models with no deterioration in performance. Taken together, these results suggest that SERF-10T Hybrid model based multipliers are suited for ultra low power design and fast computation at smaller geometry sizes.
This paper examines previously overlooked, but a highly effective, optimization approach to designing transimpedance OEIC receivers based on heterojunction bipolar and field-effect transistors (HBT's & HFET's) with high sensitivity and maximally flat frequency response. It is shown that the 3-dB bandwidth of amplifiers involving single-transistor common-emitter (CE) and common-source (CS) input stages, and the corresponding cascoded input stages can be universally expressed as f3-dB g 1/27~d~'(c,, + C L ) R~, where T' is the effective transit time of the transistor including the effect of the photodetectors capacitance, c p is the feedback capacitance of the transistor, C L is the capacitance in parallel to the collector or drain effective load conductance ( Q L ) , and Rf is the feedback resistance of the amplifier that ensures a much greater than unity loop-gain. The gain-bandwidth product can ako be universally expressed as R f x f3-dB g gm/&rgLci,, where gm is the transconductance of the transistor and cin is the total capacitance appearing at the input of the respective amplifier. For the single-transistor CE and CS input stages the dependence of the optimum values of Rf on i j~ can be expressed as R f = 2r'(c, + C L ) / (~L T ' + e,)', whereas for the corresponding cascoded input stages the same expression also applies but with c,, = 0 in the denominator. Since designing high sensitivity OEIC receivers require high values of R f and correspondingly low values of g~, thus it follows that amplifying transistors must be operated at the lowest possible current but without degradation of their high frequency performance. A low-value of the base or gate bias current also ensures a low level of shot noise thus further enhancing the sensitivity. Because of a low gm to drain current ratio in HFET's, receivers involving only the cascoded input stage, and not the single-transistor CS input stage, are capable of providing both high sensitivity and high bandwidth. In contrast, receivers based on HBT's involving either the simple CE input stage or the cascoded input stage are capable of providing both high sensitivity and high bandwidth. Design examples, using HBT's and HFET's with intrinsic unity current gain frequency fr =160 GHz and very low-capacitance msm photodetectors, indicate that high-speed receivers can be realized with bandwidth f 3 -d e g 20 GHz, and sensitivity as high as -28.7 dBm.
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