Leakage current reduction in finfet based 6T SRAM cell for minimizing power dissipation in nanoscale memories

Gupta, Vishal; Khandelwal, Saurabh; Raj, Balwinder; Gupta, Rakesh

doi:10.1109/nuicone.2015.7449596

Cited by 5 publications

(4 citation statements)

References 7 publications

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“…The only difference observed in the I-V curve is that the samples delivered different magnitude of current with the same applied input voltage. This variation in the data sets for I-V characterisation of the samples is expected and shows the process and parametric variations motivated by the imperfection in manufacturing of the devices [77,83].…”

Section: Resultsmentioning

confidence: 78%

“…samples deliver different magnitude of current with the same applied input voltage). This difference in the data sets is not unexpected and reveals the process and parametric variation motivated by the imperfection in manufacturing of the device [77]. To improve clarity, we present the results of one device for further hysteresis analysis.…”

Section: Resultsmentioning

confidence: 89%

“…However, a difference in the dark current with respect to the same input voltage (non-overlapping hysteresis curve) for all the 4 samples has been observed which is expected due to process variation at the time of device manufacturing and parametric variation at time t = 0 s [84]. This process variation is defined by intradie process variations as the samples included in this analysis shared the same substrate [77]. Also, the variation in the dark current was observed at t = 0 s and defined as a spatial parametric variation [84].…”

Section: Resultsmentioning

confidence: 93%

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Investigation of hysteresis in hole transport layer free metal halide perovskites cells under dark conditions

et al. 2020

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Recent research is a testimony to the fact that perovskite material based solar cells are most efficient since they exhibit high power conversion efficiency and low cost of fabrication. Various perovskite materials display hysteresis in their current-voltage characteristic which accounts for memory behaviour. In this paper, we demonstrate efficient non-volatile memory devices based on hybrid organic-inorganic perovskite (CH 3 NH 3 PbI 3 ) as a resistive switching layer on a Glass/Indium Tin Oxide (ITO) substrate. Our perovskite solar cells have been developed over the fully solution processed electron transport layer (ETL) which is a combination of SnO 2 and mesoporous (m)-TiO 2 scaffold layers. Hysteresis behaviour was observed in the current-voltage analysis achieving high ratio of ON & OFF current under dark and ambient conditions. Proposed perovskite-based Glass/ITO/SnO 2 /m-TiO 2 /CH 3 NH 3 PbI 3 /Au device has a hole transport layer (HTL) free structure, which is mainly responsible for a large ratio of ON & OFF current. The presence of voids in the scaffold m-TiO 2 layer are also accountable for increasing electron/hole path length which escalates the recombination rate at the surface of the ETL/perovskite interface resulting in large hysteresis in the I-V curve. This memristor device operates at a low energy due to SnO 2 layer's higher electron mobility and wide energy band gap. Our experimental results also show the dependency of voltage scan range & rate of scanning on the hysteresis behaviour in dark conditions. This memristive behaviour of the proposed device depicts drift in hysteresis loop with respect to the number of cycles, which would have a significant impact in neuromorphic applications. Moreover, due to the identical fabrication process of the proposed perovskite-based memristor device and perovskite solar cells, this device could be integrated inside a photovoltaic array to work as a power-on-chip device, where generation and computation could be possible on the same substrate for memory and neuromorphic applications.

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Section: Resultsmentioning

confidence: 78%

Section: Resultsmentioning

confidence: 89%

Section: Resultsmentioning

confidence: 93%

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Investigation of hysteresis in hole transport layer free metal halide perovskites cells under dark conditions

et al. 2020

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“…Then, the value of the written data is changed and the operation is repeated until all the combinations of the different memory words have been applied to the array. Note that due to parametric process variations of the memory bitcell [22], [23], this operation is typically repeated multiple times to filter out noise which causes the traced current of the bitcell array to alternate even when the same data stored in different words. Finally, correlation analysis is performed by estimating the current for each data combination (stored and overwritten) and by finding its correlation to the measured current.…”

Section: Power Analysis Of a 6t Sram Arraymentioning

confidence: 99%

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

et al. 2021

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Side-channel attacks constitute a concrete threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with 6T SRAM macrocells often dominate the area and power consumption of these SoCs. Regardless of the computational platform, the side-channel sensitivity of low-hierarchy cache memories can incur significant overhead to protect the memory content (i.e., data encryption, data masking, etc.). In this manuscript, we provide a silicon proof of the effectiveness of a low cost side-channel attack protection that is embedded within the memory macro to achieve a significant reduction in information leakage. The proposed solution incorporates low-cost impedance randomization units, which are integrated into the periphery of a conventional 6T SRAM macro in fine-grain memory partitions, providing possible protection against electromagnetic adversaries. Various blocks of unprotected and protected SRAM macros were designed and fabricated in a 55 nm test-chip. The protected ones had little as 1% area overhead and less than 5% performance and power penalties compared to a conventional SRAM design. To evaluate the security of the proposed solution, we applied a robust mutual information metric and an adaptation to the memory context to enhance this evaluation framework. Assessment of the protected memory demonstrated a significant information leakage reduction from 8 bits of information exposed after only 100 cycles of attack to less than ∼1.5 bits of mutual information after 160K traces. The parametric nature of the protection mechanisms are discussed while specifying the proposed design parameters. Overall, the proposed methodology enables designs with higher security-level at a minimal cost.

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Comparative Study of CMOS and FinFET-Based SRAM Cell Using SVL Technique

Sharma

Birla

2021

Micro-Electronics and Telecommunication Engineering

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Leakage current reduction in finfet based 6T SRAM cell for minimizing power dissipation in nanoscale memories

Cited by 5 publications

References 7 publications

Investigation of hysteresis in hole transport layer free metal halide perovskites cells under dark conditions

Investigation of hysteresis in hole transport layer free metal halide perovskites cells under dark conditions

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Comparative Study of CMOS and FinFET-Based SRAM Cell Using SVL Technique

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