Design and analysis of DC gain and transconductance boosted recycling folded cascode OTA

Akbari, Meysam; Biabanifard, Sadegh; Asadi, Shahrouz; Yagoub, M.C.E.

doi:10.1016/j.aeue.2014.05.007

Cited by 72 publications

(31 citation statements)

References 8 publications

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“…However, the bulksource transconductance is smaller than the gate-source transconductance and may not be sufficient in some cases. Therefore, several techniques for enhancing transconductance of the FC and current mirror (CM) amplifiers, such as multipath A c c e p t e d M a n u s c r i p t scheme (Zhao, Fang, and Xu 2012;Akbari, Biabanifard, Asadi, and Yagoub 2014) and current shunt technique (Lin, Wu, and Tsai 2007;Le and Lee 2009), can be used as the first-stage configuration in weak inversion region. Also, the Gm-C compensation technique in (Chan and Chen 2003) shows that this technique can be utilized to achieve stability of the two-stage OTA with the some multipath input stage structures (Akbari and Hashemipour 2015).…”

Section: Introductionmentioning

confidence: 99%

A two-stage rail-to-rail current mirror OTA for ultra-low-power applications

Akbari

Nazari

2015

International Journal of Electronics Letters

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In this letter an ultra-low-power, ultra-low-voltage CMOS operational transconductance amplifier (OTA) with full rail-to-rail input/output swing is presented. The proposed two-stage OTA is based on the bulk-driven current mirror (CM) amplifier topology with Gm-C frequency compensation technique.In addition, a transconductance boosting technique is used to enhance performance of the CM input stage structure. Simulation results in 0.18 μm CMOS technology show the proposed OTA achieves a 85.8 dB DC gain and a gain-bandwidth of 21.9 kHz while driving a 15 pF load. The amplifier consumes 292 nW @ 0.5 V which makes it suitable for low-power applications.

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Section: Introductionmentioning

confidence: 99%

A two-stage rail-to-rail current mirror OTA for ultra-low-power applications

Akbari

Nazari

2015

International Journal of Electronics Letters

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“…For conventional structures, the low‐voltage regime and technology advancements hamper the development of miniaturized amplifiers. In contrast, multistage amplifiers has been reported to possess excellent response regarding advancements of CMOS technology . We know that over the past years, because of technology advancements, the supply voltage has undergone major reduction without any significant intervention on threshold voltage.…”

Section: Introductionmentioning

confidence: 99%

A high‐performance CMOS four‐stage amplifier

Zanjani

Asiyabi

Biabanifard³

2019

Int J Numerical Modelling

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In this paper, we theoretically propose and mathematically describe an effective four‐stage structure in Complementary metal‐oxide‐semiconductor (CMOS) technology based on differential block feedback. The special architecture of frequency compensation network improves frequency response with very small value of compensation capacitor, which results in low die area occupation. The presented novel and simple four‐stage structure is frequency compensated just via single Miller capacitor and a differential block. Symbolical transfer function is calculated, and circuit dynamics are introduced. To well explain theoretical description, the proposed configuration at circuit level is simulated using Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.18‐μm CMOS technology and HSPICE circuit simulator. The proposed configuration and corresponding circuit benefits from circuit simplicity and low die‐area occupation. The frequency compensation network forms two Miller loops with negative loop gains. Feedback paths are amplified via differential block while feedforward paths are attenuated, leads to improving frequency response compare with conventional structures. Ample simulation results are in good agreement with theoretical description. Leveraging the concept and method proposed four‐stage amplifier exhibits 170 dB, 8.12 MHz, and 90° as direct current (DC) gain, Gain‐BandWidth Product (GBW), and Pase Margin (PM), respectively. The supply voltage is set to 1.8 V, while the simulated circuit consumes 380 μW.

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“…And ring oscillator is a circuit usually uses transistors without using passive elements [4]. The main reason of the tendency to design full transistor CMOS circuits is the ability of easy integration with absence of passive elements which reduces the die area [12][13][14][15][16][17][18][19][20]. The most significant feature of a ring oscillator is lower cost due to lower die area and design simplicity [1,4,5].…”

Section: Introductionmentioning

confidence: 99%