The intrinsic interface traps associated with thin (∼100–400Å) thermal oxides on silicon have been characterized with reference to different oxidation and annealing conditions using the quasi‐static capacitance‐voltage technique. For unannealed oxides, the interface trap distribution profiles exhibit peak structures in the lower half of silicon bandgap. A systematic dependence of the interface trap density on the oxidation variables was observed. A lower midgap density results for higher oxidation temperature, lower oxygen partial pressure in the ambient, and thicker oxide. For thin oxides, postoxidation annealing in nitrogen may decrease or increase the interface trap density depending on the anneal temperature. However, postmetallization annealing in a hydrogen atmosphere was found to be very effective in eliminating the interface traps for thin oxides. The residual interface traps exhibit a U‐shaped distribution over the bandgap and the midgap density shows no significant dependence on the oxide thickness or pre‐anneal density.