Density and Energy Distribution of Interface States in the Grain Boundaries of Polysilicon Nanowire

Abstract

Wafer-scale fabrication of semiconductor nanowire devices is readily facilitated by lithography-based top-down fabrication of polysilicon nanowire (P-SiNW) arrays. However, free carrier trapping at the grain boundaries of polycrystalline materials drastically changes their properties. We present here transport measurements of P-SiNW array devices coupled with Kelvin probe force microscopy at different applied biases. By fitting the measured P-SiNW surface potential using electrostatic simulations, we extract the longitudinal dopant distribution along the nanowires as well as the density of grain boundaries interface states and their energy distribution within the band gap.

Potential barrier height at the grain boundaries of a poly-silicon nanowire

“…Previous works for bulk P-Si reported a 'U'-shape energy distribution of GBIS within the band gap, with di↵erent peak densities ranging from 4 ⇥ 10 13 to 10 14 cm 2 eV 1 . [20,21] A recently published paper by Amit et al, [14] showed that this is the case in nanostructures as well. The acceptor and donor interface states were found to have a 'U'-shape distribution as described by the following expressions:…”

“…Recently, a low cost, top-down approach of poly-crystalline silicon nanowires (P-SiNWs) synthesis was demonstrated, using a classical fabrication method commonly used in microelectronic industry -the socalled sidewall spacer technique. [11,12,13,14] This top-down approach was previously demonstrated as a good method for biosensor fabrication for several analytes, all in which, a detection limit of femto-molar (fM) level was observed. [15,1,16,17] The main di↵erence between single crystalline silicon (SC-Si) and poly crystalline silicon (PC-Si) is charge trapping at Grain Boundaries (GBs) in the latter.…”

“…Using numerical electrostatic simulations, the GBIS distribution was determined to have a 'U'-shape distribution within the energy gap. [14] However, these results were based on a mean-distribution approach for GB simulations, which was used to simplify the complexity involved in introducing a polycrystalline material into a technology computer aided design (TCAD) simulation. The GBIS characteristics are crucial for the design of a P-Si based device, since the trapping of free carriers at the interface states results in a critical level of doping, below which the silicon becomes fully depleted.…”

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

“…Several works have exploited numerical simulations to investigate the effect of grain boundaries on variability in nanowires [340][341][342][343][344][345] and 3D NAND devices [346,347]. However, several important features of such models still have to be assessed, such as the grain size [348,349], the density and energy distribution of grain boundary traps [350,351], and the mobility degradation and conduction process at the grain boundaries [352,353]. …”

Electrical properties of self-aligned gate-all-around polycrystalline silicon nanowires field-effect transistors

“…These high cost fabrication methods are not compatible with mass production. However, polycrystalline silicon SiNWs (poly-SiNWs) synthesis using sidewall spacer top down method [19][20][21] seems to be a lower cost alternative, fully compatible with planar complementary metal oxide semiconductor (CMOS) silicon technology.…”