Potential barrier height at the grain boundaries of a poly-silicon nanowire

Abstract

We present measurements of the potential barrier height and its dependence on grain size in poly-silicon nanowire (P-SiNW) arrays. Measurements conducted using Kelvin probe force microscopy coupled with electrostatic simulations, enabled us also to extract the density of the grain boundary interface states and their energy distribution. In addition it was shown that the barrier height scales with the grain size as the square of the grain radius.

Studies on structural, optical, and photoelectric properties of CdS1-xSexfilms fabricated by selenization of chemical bath deposited CdS films

“…These trapping states can trap and immobilize the carriers, resulting in the traps being charged. The charged traps will create a grain boundary barrier which impedes the motion of the carriers, thereby reducing their mobility [20,21]. Increasing the grain size can effectively reduce the amount of the trapping states, which is beneficial to the transport of the carriers.…”

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

“…Several works have exploited numerical simulations to investigate the effect of grain boundaries on variability in nanowires [340][341][342][343][344][345] and 3D NAND devices [346,347]. However, several important features of such models still have to be assessed, such as the grain size [348,349], the density and energy distribution of grain boundary traps [350,351], and the mobility degradation and conduction process at the grain boundaries [352,353]. …”