Demonstration of Ultra-Low Voltage and Ultra Low Power STT-MRAM designed for compatibility with 0x node embedded LLC applications

Jan, Guenole; Thomas, Luc; Le, S.; Lee, Yuan-Jen; Liu, Huanlong; Zhu, Jian; Iwata-Harms, Jodi; Patel, Sahil; Tong, Ru-Ying; Sundar, V.; Serrano-Guisan, S.; Shen, Dongna; He, Renren; Haq, Jesmin; Teng, Zhongjian; Lam, V.; Yang, Yi-feng; Wang, Yu-Jen; Zhong, Tom; Fukuzawa, H.; Wang, Po-Kang

doi:10.1109/vlsit.2018.8510672

Cited by 27 publications

(15 citation statements)

References 1 publication

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“…The use of Hopfield like recurrent neural networks (RNNs) with memristive devices has already been successfully demonstrated in a variety of tasks (Milo et al, 2017;Wang et al, 2020b). As an example of memristive based coupled oscillator network, Ignatov et al (2017) used a network of self-sustained van der Pol oscillators coupled (Kim et al, 2011;Lee et al, 2011) 10 11 (Kim et al, 2010) 10 12 (Saida et al, 2017) > 10 15 (Udayakumar et al, 2013) SET/RESET time 100 ps (Torrezan et al, 2011) >100 ns, 10 ns 20 ns (Jan et al, 2018) 30 ns, 30 ns 85 ps (Choi et al, 2016) (IRDS, 2020) 3 ns (Kitagawa et al, 2012) (Francois et al, 2019) Read current 100 pA (Luo et al, 2016) 25 µA (De Sandre et al, 2010) 20 µA (Kitagawa et al, 2012) 0.8 nA (Bruno et al, 2016), device diameter 300 nm)…”

Section: Memristive Neural Networkmentioning

confidence: 99%

Adaptive Extreme Edge Computing for Wearable Devices

et al. 2021

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Wearable devices are a fast-growing technology with impact on personal healthcare for both society and economy. Due to the widespread of sensors in pervasive and distributed networks, power consumption, processing speed, and system adaptation are vital in future smart wearable devices. The visioning and forecasting of how to bring computation to the edge in smart sensors have already begun, with an aspiration to provide adaptive extreme edge computing. Here, we provide a holistic view of hardware and theoretical solutions toward smart wearable devices that can provide guidance to research in this pervasive computing era. We propose various solutions for biologically plausible models for continual learning in neuromorphic computing technologies for wearable sensors. To envision this concept, we provide a systematic outline in which prospective low power and low latency scenarios of wearable sensors in neuromorphic platforms are expected. We successively describe vital potential landscapes of neuromorphic processors exploiting complementary metal-oxide semiconductors (CMOS) and emerging memory technologies (e.g., memristive devices). Furthermore, we evaluate the requirements for edge computing within wearable devices in terms of footprint, power consumption, latency, and data size. We additionally investigate the challenges beyond neuromorphic computing hardware, algorithms and devices that could impede enhancement of adaptive edge computing in smart wearable devices.

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Section: Memristive Neural Networkmentioning

confidence: 99%

Adaptive Extreme Edge Computing for Wearable Devices

et al. 2021

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“…Some works suggest that SOT-MRAM requires a lower write time and a lower write energy than STT-MRAM [40][41][42][43]. On the other hand, the results presented in Reference [26] show that VCMA-MeRAMs outperform STT-MRAM in terms of area, speed and energy consumption.…”

Section: Wl Slmentioning

confidence: 99%

Magnetic Tunnel Junction Applications

Maciel

Marques

Naviner

et al. 2019

Sensors

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Spin-based devices can reduce energy leakage and thus increase energy efficiency. They have been seen as an approach to overcoming the constraints of CMOS downscaling, specifically, the Magnetic Tunnel Junction (MTJ) which has been the focus of much research in recent years. Its nonvolatility, scalability and low power consumption are highly attractive when applied in several components. This paper aims at providing a survey of a selection of MTJ applications such as memory and analog to digital converter, among others.

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“…We performed circuit simulation for two types of emerging memories with distinctive resistance ranges. For MRAM memory cells we assumed 1 k for LRS and 2.5 k for HRS (based on assumptions of MTJ CD ∼ 80nm, RA ∼ 5 .µm 2 , and TMR ∼ 150% [28], [29]). Respective values for PCRAM of 30 k for LRS and 2 M for HRS were assumed based on [30].…”

Section: B Impact Of Design Parameters and Parasitic Resistancementioning

confidence: 99%

Design and Measurement Requirements for Short Flow Test Arrays to Characterize Emerging Memories

Brozek

Ciplickas

2019

IEEE J. Electron Devices Soc.

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Emerging non-volatile memories are becoming increasingly attractive for embedded and storage-class applications. Among the development challenges of Back-End integrated memory cells are long learning cycles and high wafer cost. We propose a short-flow based approach for characterization of Memory Arrays using a Cross-Point Array structure and highly parallel Parametric Test. A detailed analysis of design requirements and testability, including inverse circuit simulation, confirms feasibility of the approach to reduce Turn-Around Time and development costs.

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Demonstration of Ultra-Low Voltage and Ultra Low Power STT-MRAM designed for compatibility with 0x node embedded LLC applications

Cited by 27 publications

References 1 publication

Adaptive Extreme Edge Computing for Wearable Devices

Adaptive Extreme Edge Computing for Wearable Devices

Magnetic Tunnel Junction Applications

Design and Measurement Requirements for Short Flow Test Arrays to Characterize Emerging Memories

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