“…The process that leads to a memristive-based neuromorphic system includes undoubtedly many challenges at device level, e.g., optimisation of the materials, scaling of the device, reduction of the device variability, read and write speed, and energy consumption, but also at circuit and system level, e.g., the circuits to address, program, and read the devices and to interface them with the other parts of the chip and with the external world, and the routing of the events [96]. However, to design a hybrid CMOS-memristive hardware, these challenges cannot be tackled separately, they need to be framed in a holistic approach where everything is developed together [5,97]. Moreover, also the learning algorithms should be selected not only according to the intended application, but they also need to be adapted in order to best exploit the features of the memristive devices [5,98].…”