Design and Measurement Requirements for Short Flow Test Arrays to Characterize Emerging Memories

Abstract

Emerging non-volatile memories are becoming increasingly attractive for embedded and storage-class applications. Among the development challenges of Back-End integrated memory cells are long learning cycles and high wafer cost. We propose a short-flow based approach for characterization of Memory Arrays using a Cross-Point Array structure and highly parallel Parametric Test. A detailed analysis of design requirements and testability, including inverse circuit simulation, confirms feasibility of the approach to reduce Turn-Around Time and development costs.