Demonstration of Convolution Kernel Operation on Resistive Cross-Point Array

Gao, Ligang; Chen, Pai-Yu; Yu, Shimeng

doi:10.1109/led.2016.2573140

Cited by 134 publications

(74 citation statements)

References 17 publications

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“…15. The edge extractions described in this step are also a frequent layer of convolutional neural networks (CNNs or ConvNets) 18,49,50 , which is the most computationally expensive step in the networks. Compared to previously reported convolutions operating with binary inputs, binary weights and series readout 18 , our image filtering procedure included both analogue convolution matrices and analogue inputs, as well as parallel readout of 10 feature maps.…”

Section: Nature Electronicsmentioning

confidence: 99%

Analogue signal and image processing with large memristor crossbars

et al. 2017

Nat Electron

1,008

753

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Section: Nature Electronicsmentioning

confidence: 99%

Analogue signal and image processing with large memristor crossbars

et al. 2017

Nat Electron

1,008

753

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“…A common method for implementing the convolution layer of the CNN is extracting the feature maps into smaller sizes through CBA bit lines (BLs), whereas a portion of the input image is fed into the CBA through word lines (WLs), which is commonly regarded as applying a kernel (or filter). In the neuromorphic hardware using the S‐CBA, implementing such kernel functions can be readily understood from SI Figure S1 and S2, Supporting Information, of which details are explained in SI‐I (basic idea of applying the S‐CBA to a kernel using an inverse mapping method).…”

Section: Resultsmentioning

confidence: 99%

Kernel Application of the Stacked Crossbar Array Composed of Self‐Rectifying Resistive Switching Memory for Convolutional Neural Networks

Kim

et al. 2019

Advanced Intelligent Systems

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Herein, a feasible method is provided for circuit implementation of the convolutional neural network (CNN) in neuromorphic hardware using the multiple layers‐stacked resistance switching random access memory (ReRAM). The specific ReRAM is accompanied by self‐rectification functionality. The single‐input multiple‐output (SIMO) scheme is an optimum method in the extraction of the features of a letter with a versatile selection of the intended features, whereas the multiple‐input single‐output (MISO) scheme provides a highly efficient method to extract the features from the color image, which is composed of several component color images. The Pt/HfO2−x/TiN‐based self‐rectification ReRAM that is integrated into the sidewalls of the two‐layer structure provides a sound framework for the circuit implementation of the SIMO and MISO schemes. The appropriate selection of the kernels for image compression and feature extraction greatly facilitates the CNN in neuromorphic hardware.

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“…[61,63,64] For example, a fully connected layer can be directly mapped on one RRAM array or partitioned and implemented onto a few smaller arrays. [63,65,66] For long short term memory (LSTM) networks, the synaptic weights in an LSTM layer toward input gate, output gate, and forget gate can be deployed on different RRAM arrays. [63,65,66] For long short term memory (LSTM) networks, the synaptic weights in an LSTM layer toward input gate, output gate, and forget gate can be deployed on different RRAM arrays.…”

Section: Rram Basics and Rram Array For Inferencementioning

confidence: 99%

Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

Yan

Qiao

et al. 2019

Advanced Intelligent Systems

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In‐memory computing is a computing scheme that integrates data storage and arithmetic computation functions. Resistive random access memory (RRAM) arrays with innovative peripheral circuitry provide the capability of performing vector‐matrix multiplication beyond the basic Boolean logic. With such a memory–computation duality, RRAM‐based in‐memory computing enables an efficient hardware solution for matrix‐multiplication‐dependent neural networks and related applications. Herein, the recent development of RRAM nanoscale devices and the parallel progress on circuit and microarchitecture layers are discussed. Well suited for analog synapse and neuron implementation, RRAM device properties and characteristics are emphasized herein. 3D‐stackable RRAM and on‐chip training are introduced in large‐scale integration. The circuit design and system organization of RRAM‐based in‐memory computing are essential to breaking the von Neumann bottleneck. These outcomes illuminate the way for the large‐scale implementation of ultra‐low‐power and dense neural network accelerators.

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Demonstration of Convolution Kernel Operation on Resistive Cross-Point Array

Cited by 134 publications

References 17 publications

Analogue signal and image processing with large memristor crossbars

Analogue signal and image processing with large memristor crossbars

Kernel Application of the Stacked Crossbar Array Composed of Self‐Rectifying Resistive Switching Memory for Convolutional Neural Networks

Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

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