Demonstration of a Nanosheet FET With High Thermal Conductivity Material as Buried Oxide: Mitigation of Self-Heating Effect

Rathore, Sunil; Jaisawal, Rajeewa Kumar; Kondekar, P. N.; Bagga, Navjeet

doi:10.1109/ted.2023.3241884

Cited by 21 publications

(8 citation statements)

References 31 publications

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“…The higher order coefficients of the transconductances g m2 and g m3 are important for achieving linearity [27] as well as the extrapolated gate voltages VIP 2 and VIP 3 , which indicate when the fundamental tone amplitude is equal to the second and third harmonic, expressed in equations ( 6) and (7). The third order input intercept point (IIP 3 ) is the extrapolated input power at which the first and third harmonic powers are equal, specified in equation (8) where, R S = 50 ohm, used for calculating these parameters in analog RF applications [28]. IMD 3 is the third order intermodulation distortion, which represents the extrapolated current at which the first and third intermodulation harmonic currents are equal specified in equation (9).…”

Section: Non-linearity and Distortion Analysismentioning

confidence: 99%

“…Moreover, in recent times, development of nanosheet and forksheets come into picture that performs very well under deep sub-micron technologies. Sunil et al, proposed a buried-oxide engineered nanosheet FET that suppresses self-heating effect [8]. However, in this work, device optimization is carried out on the basis of electrical parameters such as I D , g m , and capacitance(s) among the four proposed devices: D1, D2, D3, and D4, with respect to variation in fin height and width.…”

Section: Introductionmentioning

confidence: 99%

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Temperature analysis of TG FinFET on electrical, RF and distortion parameters for wireless applications

Ansari,

Jha,

Sharma

et al. 2023

Eng. Res. Express

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This article proposes four Triple Gate (TG) FinFET structures with variations in fin height and fin width with 22 nm gate length on SOI substrate. The four different structures are presented in terms of (fin height, fin width) such as D1(20 nm, 22 nm), D2(10 nm and 20 nm), D3(8 nm and 18 nm), and D4(6 nm and 16 nm). The objective is to investigate the effect of fin dimensions on the DC characteristics of the FinFET structures. Upon analyzing the DC characteristics, it is observed that D1 had an order of leakage current of 10−10 A, while D4 had 10−14 A. Additionally, D1 and D4 exhibited a change in subthreshold swing (SS) of 30%, with D1 having a value of 78.1 mV/decade and D4 having 60.0 mV/decade. The RF metric gate-to-gate capacitance reduced from D1 to D4 by 90%, and the threshold voltage of D4 was found to be 0.342 V. Based on these findings, D4 structure had better optimized results. Furthermore, temperature is varied on the D4 structure from 300 K to 500 K; electrical, RF, and distortion parameters were analyzed thoroughly. It is observed that the RF parameters reduced while the temperature increased, with transconductance frequency product (TFP), gain frequency product (GFP), and cut-off frequency (fT) decreasing by 92.1%, 98.5%, and 92.4%, respectively. However, the distortion parameters slightly increased with an increase in temperature. VIP2, VIP3, gm2, gm3, and IMD3 decreased, indicating that the device performance in wireless applications increases with increasing temperature. Overall, findings suggest that the D4 (6 nm and 16 nm) structure is a promising candidate for wireless applications, especially those that require high-temperature operation.

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Section: Non-linearity and Distortion Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Temperature analysis of TG FinFET on electrical, RF and distortion parameters for wireless applications

Ansari,

Jha,

Sharma

et al. 2023

Eng. Res. Express

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“…Currently, the ways of alleviating heat dissipation are mainly based on the engineering interface thermal conductivity between 2D materials and dielectric substrates as well as employing encapsulation techniques on the surface of the 2D materials. ,− In interface engineering, researchers are inclined to replace traditional SiO 2 with a high thermal conductive insulating layer . For instance, Liu et al utilized near equilibrium PECVD technology to grow a large-area smooth, atomic level flat 2D-BN thin film (with a thickness of 20–200 nm) as a dielectric layer on the SiO 2 /Si surface. Subsequently, they used CVD to grow WSe 2 on the 2D-BN layer as the channel material .…”

Section: Introductionmentioning

confidence: 99%

Self-Heating Effect in a MoS₂ Field-Effect Transistor and Improved Heat Dissipation by the BN Capping Layer

Dang,

Huangfu,

Hossain

et al. 2024

ACS Appl. Electron. Mater.

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The inefficient heat dissipation in two-dimensional (2D) semiconductor-based field-effect transistors (FETs) hampers their electrical performance and reliability. In this study, we address this issue by experimentally investigating the factors influencing the self-heating of MoS 2based 2D FETs and enhancing the heat dissipation of MoS 2 -based 2D FETs using a high thermal conductivity BN capping layer. The results demonstrate a significant reduction in the negative differential resistance (NDR) with 2D BN encapsulation, leading to improved electrical properties, such as increased saturation current density (average increase of 15.42%, maximum increase of 42%), and device saturation power density (average increase of 15.77%). This research sheds light on the self-heating effect in 2D FET devices and provides valuable insights for enhancing heat dissipation in 2D FETs through the use of high thermal conductivity insulator capping materials.

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“…As a result, bulk-silicon transistors are experiencing the same difficulties as MOSFETs due to the presence of Short Channel Effects (SCEs) [1]. To minimize these SCEs, novel device architectures such as Double gate (DG) FET [2][3][4], FinFET [5][6][7], Quadraple gate FET [8,9], and gate all around (GAA) FET [10][11][12][13][14] are introduced in the literature. However, DG FETs poses a challenge in the symmetrical alignment of the front and back gates.…”

Section: Introductionmentioning

confidence: 99%

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Mudidhe,

Nistala

2023

Phys. Scr.

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The GAA FET has emerged as a promising device due to its excellent control over short-channel effects and improved electrostatic control. This manuscript presents the analytical modelling for the Dual Material Graded Channel (DMGC) Cylindrical GAA FET to characterize the drain current in linear, saturation, as well as subthreshold regions. The model incorporates the effect of supply voltage, radius, and thickness of oxide layer on the device enabling a comprehensive analysis of the device behaviour. The influence of subthreshold swing is also presented. Next, the analysis is extended to investigate the important analog performance parameters that includes transconductance and output conductance. The validation of the analytical model across a wide range of operating conditions with the simulated data is performed and observed to be a close match. Building upon the insights gained from the analytical modelling, a common source amplifier based on the DMGC CGAA FET is designed. The amplifier's performance has been optimized by carefully selecting the biasing conditions and a maximum gain value of 7.745 is achieved. Further, an improvement of 42.28% in output voltage is observed for DMGC in comparison with SMGC making it a promising device for high-performance integrated circuit design.

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Demonstration of a Nanosheet FET With High Thermal Conductivity Material as Buried Oxide: Mitigation of Self-Heating Effect

Cited by 21 publications

References 31 publications

Temperature analysis of TG FinFET on electrical, RF and distortion parameters for wireless applications

Temperature analysis of TG FinFET on electrical, RF and distortion parameters for wireless applications

Self-Heating Effect in a MoS₂ Field-Effect Transistor and Improved Heat Dissipation by the BN Capping Layer

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

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Demonstration of a Nanosheet FET With High Thermal Conductivity Material as Buried Oxide: Mitigation of Self-Heating Effect

Cited by 21 publications

References 31 publications

Temperature analysis of TG FinFET on electrical, RF and distortion parameters for wireless applications

Temperature analysis of TG FinFET on electrical, RF and distortion parameters for wireless applications

Self-Heating Effect in a MoS2 Field-Effect Transistor and Improved Heat Dissipation by the BN Capping Layer

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Contact Info

Product

Resources

About

Self-Heating Effect in a MoS₂ Field-Effect Transistor and Improved Heat Dissipation by the BN Capping Layer