Temperature analysis of TG FinFET on electrical, RF and distortion parameters for wireless applications

Abstract

This article proposes four Triple Gate (TG) FinFET structures with variations in fin height and fin width with 22 nm gate length on SOI substrate. The four different structures are presented in terms of (fin height, fin width) such as D1(20 nm, 22 nm), D2(10 nm and 20 nm), D3(8 nm and 18 nm), and D4(6 nm and 16 nm). The objective is to investigate the effect of fin dimensions on the DC characteristics of the FinFET structures. Upon analyzing the DC characteristics, it is observed that D1 had an order of leakage current of 10−10 A, while D4 had 10−14 A. Additionally, D1 and D4 exhibited a change in subthreshold swing (SS) of 30%, with D1 having a value of 78.1 mV/decade and D4 having 60.0 mV/decade. The RF metric gate-to-gate capacitance reduced from D1 to D4 by 90%, and the threshold voltage of D4 was found to be 0.342 V. Based on these findings, D4 structure had better optimized results. Furthermore, temperature is varied on the D4 structure from 300 K to 500 K; electrical, RF, and distortion parameters were analyzed thoroughly. It is observed that the RF parameters reduced while the temperature increased, with transconductance frequency product (TFP), gain frequency product (GFP), and cut-off frequency (fT) decreasing by 92.1%, 98.5%, and 92.4%, respectively. However, the distortion parameters slightly increased with an increase in temperature. VIP2, VIP3, gm2, gm3, and IMD3 decreased, indicating that the device performance in wireless applications increases with increasing temperature. Overall, findings suggest that the D4 (6 nm and 16 nm) structure is a promising candidate for wireless applications, especially those that require high-temperature operation.