Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters

Wu, Chung‐Yu; Shiau, Ming-Chuen

doi:10.1109/4.62149

Cited by 24 publications

(11 citation statements)

References 17 publications

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“…Extensions to this repeater insertion methodology have also been reported in [2] and [3]. In [2] and [4], Wu and Shiau describe a repeater implementation to reduce interconnect delay. Their method uses a linearized form of the Shichman-Hodges equations [5] at a specific operating point to determine the proper repeater insertion locations.…”

Section: Introductionmentioning

confidence: 99%

Uniform repeater insertion in RC trees

Adler¹,

Friedman²

2000

IEEE Trans. Circuits Syst. I

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Repeater insertion can be used to overcome the quadratic increase in the time required for a signal to propagate through an interconnect. A new timing model, based on short-channel equations, has been developed to characterize the signal delay through a resistive line. These analytical expressions provide the foundation for algorithms used to insert uniform repeaters into tree structures. Both local and global optimization algorithms for repeater insertion are presented. While the local optimization algorithm provides a computationally fast solution to the repeater insertion problem, the resulting circuit implementation is less power, area, and speed efficient than applying global optimization techniques. The global optimization algorithm for repeater insertion is achieved through the downhill simplex method. The circuit equations, algorithms, and software implementation of this repeater insertion system are presented in this paper.Results from these insertion methodologies improve delay from 25% to 60% versus typical cascaded buffer methodologies. Global repeater insertion further decreases delay times by up to 22% over the local repeater insertion method. The accuracy of the timing model characterizing the repeater insertion process as compared to SPICE simulations is generally within 10%. Applications of these algorithms for minimizing the signal delay through an tree, such as in data paths, and targeting signal delays through an tree, such as in clock distribution networks, are also discussed.

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Section: Introductionmentioning

confidence: 99%

Uniform repeater insertion in RC trees

Adler¹,

Friedman²

2000

IEEE Trans. Circuits Syst. I

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“…Several repeater models are proposed such as the switch-level RC model [5], the linearized form of the Shichman-Hodges equations [20], and the short-channel α-power law model [1]. Early repeater insertion algorithms ignore geometric constraints due to layout and assume that repeaters can be placed at any location derived from the mathematical analysis [4,8,12].…”

Section: Introductionmentioning

confidence: 99%

Practical repeater insertion for low power: what repeater library do we need?

Liu

Peng

Papaefthymiou

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper, we investigate the problem of repeater insertion for low power under a given timing budget. We propose a novel repeater insertion algorithm to compute the optimal repeater number and width in the discrete solution space, as defined by a given repeater library. Using our algorithm, we show that rounding the solution under the continuity assumption to the closest discrete solution candidate may result in suboptimal designs, or it may even fail to find an existing solution. Given a certain tolerance to the degradation of repeater power dissipation, we address two practical and highly important questions: (1) How coarse could the repeater size granularity be? (2) What range should the repeater size be in?Experimental results demonstrate the high effectiveness of the proposed scheme and provide valuable insights into repeater library design. Our approach achieves up to 23% power reduction in comparison to rounding-based approaches. With a 4% power degradation tolerance, repeater size granularity as coarse as 8λ can be used, reducing the library size by more than 87%. For interconnects with various wire lengths and timing targets, our investigation reveals that the range of optimal repeater sizes for low-power is limited, indicating that a low-cost small-size repeater library, if well designed, is adequate to provide high quality repeater insertion solutions.

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“…Several methods have been introduced to reduce interconnect delay so that these impedances do not dominate the delay of a critical path [1][2][3][4]. Furthermore, with the introduction of portable computers, power has become an increasingly important factor in the circuit design process.…”

Section: Introductionmentioning

confidence: 99%

Timing and power models for CMOS repeaters driving resistive interconnect

Adler

Friedman²

Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit

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A delay and power model of a CMOS inverting repeater driving a resistive-capacitive load is presented. The model is derived from Sakurai's alpha-power law and exhibits good accuracy. The model can be used to design and analyze those CMOS inverters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay and transition time and exhibit less than 27% discrepancy from SPICE for a wide variety of RC loads. Expressions are also provided for modeling the short-circuit power dissipation of a CMOS inverter driving a resistive-capacitive interconnect line which are accurate to within 15% of SPICE for most practical loads.

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Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters

Cited by 24 publications

References 17 publications

Uniform repeater insertion in RC trees

Uniform repeater insertion in RC trees

Practical repeater insertion for low power: what repeater library do we need?

Timing and power models for CMOS repeaters driving resistive interconnect

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