Timing and power models for CMOS repeaters driving resistive interconnect

Abstract

A delay and power model of a CMOS inverting repeater driving a resistive-capacitive load is presented. The model is derived from Sakurai's alpha-power law and exhibits good accuracy. The model can be used to design and analyze those CMOS inverters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay and transition time and exhibit less than 27% discrepancy from SPICE for a wide variety of RC loads. Expressions are also provided for modeling the short-circuit power dissipation of a CMOS inverter driving a resistive-capacitive interconnect line which are accurate to within 15% of SPICE for most practical loads.

Timing Optimization Through Clock Skew Scheduling

“…• The use of repeater circuit structures to drive resistive-capacitive (RC) loads. Unlike tapered buffers, repeaters are typically CMOS inverters of uniform size (drive capability) that are inserted at uniform intervals along an interconnect line [8,42,43,44,45,46,47]. • A different timing discipline such as asynchronous timing [17,48,49].…”

“…45)]. Therefore, the clock skew T Skew (i, j) is defined and is of primary practical use for sequentiallyadjacent pairs of registers R i YR j , that is, for local data paths.…”