Defect tolerance on the Teramac custom computer

Culbertson, W. Bruce; Amerson, R.; Carter, R.J.; Kuekes, Philip J.; Snider, Greg

doi:10.1109/fpga.1997.624611

Cited by 93 publications

(53 citation statements)

References 14 publications

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“…In a reconfigurable architecture, recovery entails isolating defective module(s) and incorporating spare structures as needed. Support for reconfiguration can be achieved at various granularities, from ultrafine grain systems [7,8] that have the ability to replace individual logic gates to coarser designs that focus on isolating entire processor cores [1,2,[9][10][11][12][13][14]21]. This choice presents a trade-off between complexity of implementation and potential lifetime enhancement [15,16].…”

Section: Related Workmentioning

confidence: 99%

Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

Kim

2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/ power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

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Section: Related Workmentioning

confidence: 99%

Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

Kim

2011

JSTS:Journal of Semiconductor Technology and Science

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“…Reconfigurability has been used for years to implement new circuits after manufacture, as in commerical and research Field Programmable Gate Arrays [19,20,21,22]. It has also been used to incorporate defective circuit elements into a working, high-performance computer, the Teramac [23], by discovering the defective circuit elements after fabrication.…”

Section: Electronic Nanotechnologymentioning

confidence: 99%

What Makes a Good Molecular-Scale Computer Device?

Goldstein¹,

Rosewater

2002

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The lithographically-produced CMOS transistor has been the key technology that has enabled the information revolution. However, in the near future the limitations, both technical and economic, introduced by lithographic fabrication may inhibit further decreases in feature size. Chemically assembled electronic nanotechnology (CAEN) is a promising alternative to CMOS for constructing circuits with device sizes in the tens of nanometers, far smaller than is thought possible using lithography. In this paper we examine and contrast the constraints imposed by lithographic versus CAEN fabrication; the key limitation is that three-terminal devices, such as transistors, will be impractical at the nanoscale. We demonstrate that these constraints can be satisfied by outlining an architecture that uses only two-terminal CAEN devices to compute without transistors. One crucial requirement of this design circuit is that it be able to restore signals to a reference state without transistors. We present preliminary results for a molecular latch, constructed from molecular resonant tunneling diodes (RTDs) that can perform signal restoration, I/O isolation, and voltage buffering without transistors at the nanoscale.

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“…The concept here is to use spare resources that are naturally present in an FPGA design as no FPGA design uses all of the FPGAs resources. Doing a new place-androute is very computationally expensive and uses much resources and is, therefore, often completed off-chip using standard synthesis tools (the Teramac project [2]). However, the Cell Matrix [15] provides an example of an on-chip solution incorporating a complex cell solution.…”

Section: Configurationmentioning

confidence: 99%

Evolving Redundant Structures for Reliable Circuits - Lessons Learned

Djupdal

Haddow

2007

Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)

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Fault Tolerance is an increasing challenge for integrated circuits due to semiconductor technology scaling. This paper looks at how artificial evolution may be tuned to the creation of novel redundancy structures which may be applied to meet this challenge. However, as these structures are unknown it is a challenge in itself to tune evolution to create them. As such, no solution has yet been found. This paper provides a discussion about the issues addressed and experiments conducted and thus provides an overview of the lessons learned in this work.

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Defect tolerance on the Teramac custom computer

Cited by 93 publications

References 14 publications

Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

What Makes a Good Molecular-Scale Computer Device?

Evolving Redundant Structures for Reliable Circuits - Lessons Learned

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