Defect-free shallow P/N junction by point defect engineering

Onishi, S.; Ayukawa, A.; Uda, Keichiro; Sakiyama, K.

doi:10.1109/relphy.1992.187631

Cited by 3 publications

(1 citation statement)

References 8 publications

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“…The STI process, however, can be a major origin of stress because of the use of materials with different thermal expansion coefficients and a complicated fabrication process. [1][2][3] Therefore, in LSI manufacturing, the optimization of the STI fabrication process is very important for improving device performance, manufacturing yield, and device reliability. In this paper, in order to determine the relationship between the generated leakage current and the STI fabrication process, detailed structural observation and strain measurement around an STI structure by transmission electron microscopy (TEM) and a numerical strain simulation were carried out using transistor test structures.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of the Strain around an Isolated Shallow Trench and the Impact of Stress on LSI Device Performance

Fukumoto

Kudo

Ota

et al. 2010

Jpn. J. Appl. Phys.

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We propose a stress-controlled fabrication process for shallow trench isolation (STI) that can reduce stress-originated leakage current. In this paper, the relationships between the electrical characteristics of a transistor and the STI fabrication process parameters were obtained by measurement. Direct measurements of mechanical strain around an STI structure were executed by convergent beam electron diffraction (CBED) analysis, and mechanical strain was simulated by the finite element method (FEM). Transmission electron microscopy (TEM) analysis was also performed. It was revealed that the undesirable leakage current in a transistor was caused by a dislocation in crystal silicon, which was induced by tensile strain perpendicular to the silicon surface. We also found that the mechanical strain is controllable by optimizing the amount of recess of the gap-fill oxide in the STI structure after chemical mechanical polishing (CMP).

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Section: Introductionmentioning

confidence: 99%

Evaluation of the Strain around an Isolated Shallow Trench and the Impact of Stress on LSI Device Performance

Fukumoto

Kudo

Ota

et al. 2010

Jpn. J. Appl. Phys.

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Source/drain junction leakage current of LDD NMOSFET with various spacer materials

Jo²,

Park³

et al.

Proceedings International Conference on Microelectronic Test Structures

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The sourcddrain junction leakage currents of lightly doped drain(LDD) MOSFET for various gate sidewall spacer materials have been measured and analyzed. Since the step coverages of spacer materials and the etch rates of field oxide during the gate sidewall spacer etch process are different,the junction leakage currents are found to be different for three different spacer materials. Therefore, the comer defects formed at the boundaries between the source/drain substrate and the field oxide have different depth. The deeper the comer defects form, the more the junction leakage currents flow. The defects are generated by the damage from n+ source/drain As75 implant process following the gate sidewall spacer etch.

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