IntroductionBeyond sub-40nm NAND flash memory, MANOS (Si-SiO2-SiNx-Al2O3-Metal gate) is known as the most promising structure to substitute the floating gate (FG) cell [1]. In MANOS structure, physical properties of trapping nitride plays an important role to decide cell performance, and these are usually represented by trap (energy) level, trap density (Nt), and capture cross-section (CCS).In this study, physical properties of different trapping nitrides were extracted, and the program efficiency of MANOS cell was explained. We also showed shallow traps were generated at trapping nitride by etching damage, and this could be cured resulting great improvement of cell performance. Lastly, erasure mechanism of TiN-gate MANOS cell was discussed with some experimental and modeling results.
Results & DiscussionsTiN-gate MANOS cell was fabricated using our 60nm floating gate NAND technology. 20nm-thick TiN gate electrode was deposited on the SiO 2 (4nm)/ SiN x (8nm)/Al 2 O 3 (15nm) dielectric stack. Because of its higher work function, TiN was chosen for the gate electrode to suppress the backward tunneling during erasure. Figure 1 shows the experimental and fitting results of Vth shift of TiN-gate MANOS capacitor with different SiN x (denoted as A and B) under 13V~17V program bias range. The fitting equation is written as;where T α is the capture cross-section (CCS). Calculated Nt of Nitride A and B were 4E19cm -3 and 3.5E19 cm -3 , and CCS were 2.5E-14cm -2 and 1.8E-14cm -2 , respectively.Program speed of large cell (L/W=250x250nm 2 ) and 60nm FG cell were compared in figure 2 with their fitting results calculated from extracted Nt and CCS. The program efficiency (=∆Vth/∆Vpgm) is useful to understand MANOS cell character as physical property of traps. Measured efficiencies of both Nitride A and B are well fitted only at low field regime, while the FG cell was fitted the entire range with the constant slope (=1), since MANOS cell did not capture all tunneling current contrary to FG cell. The efficiency of MANOS cell is as low as about 0.6~0.7 in our work, and also was found in other report [2]. Program efficiency of MANOS cell was calculated with some typical Nt and CCS values in figure 3. The efficiency has maximum around 0.8 and rapidly decreases at low Nt value, because empty trap was exhausted as programming. Thus, Nt is more important for the efficiency at higher field than CCS. In fact, the difference from Nitride A and B was not significant. Figure 4 reveals the efficiency reduced as gate length scaling and became smaller at higher field, while no efficiency decay occurred as channel width (figure 5). It was reported that breakdown voltage was reduced by gate etching damage in TaN-gate MANOS cell [1]. It was thought our TiN-gate cell suffered the similar damage localized at gate edge as shown in figure 4. After curing the cell, we found the efficiency was greatly improved especially at high field, and scaling effect was disappeared as well ( figure 6).This change was clearly distinguished at hot temperature (HT)...
We derive an improved prescription for the merging of matrix elements with parton showers, extending the CKKW approach. A flavour-dependent phase space separation criterion is proposed. We show that this new method preserves the logarithmic accuracy of the shower, and that the original proposal can be derived from it. One of the main requirements for the method is a truncated shower algorithm. We outline the corresponding Monte Carlo procedures and apply the new prescription to QCD jet production in e + e − collisions and Drell-Yan lepton pair production. Explicit colour information from matrix elements obtained through colour sampling is incorporated in the merging and the influence of different prescriptions to assign colours in the large N C limit is studied. We assess the systematic uncertainties of the new method.
We report the dependence of Si–SiO2 interface trap density after Fowler–Nordheim (F/N) stress on various capping materials between gate stacks and an inter layer dielectric (ILD) in a NAND Flash memory cell. The interface trap density was characterized by charge pumping method (CPM). When the capping layer is an oxide, the Nit after F/N stress is approximately 2×1011 cm-2, which is about 50% smaller than that with a nitride layer. We found that the oxide layer causes compressive stress whereas the nitride layer causes a relatively high tensile stress in the underlying substrate by measuring the warp change of the substrate. To correlate the interface state density and data retention characteristics, we measured Vt shift after high-temperature baking. When an oxide capping layer is used, the retention characteristics of memory devices are greatly improved compared to the nitride capping case. These results show a good correlation between the interface characteristics and mechanical stress behaviors.
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