The microstructure and electrical properties were investigated for SrTiO 3 (STO) thin films deposited on Pt͞Ti͞SiO 2 ͞Si substrates by PEMOCVD. The SrF 2 phase existing in the STO films deposited at 450 ± C influences the dielectric constant, dissipation factor, and leakage current density of STO films. The dielectric constant and dissipation factor of STO films deposited at 500 ± C were 210 and 0.018 at 100 kHz, respectively. STO films were found to have paraelectric properties from the capacitance-voltage characteristics. Leakage current density of STO films at 500 ± C was about 1.0 3 10 28 A͞cm 2 at an electric field of 70 kV͞cm. The leakage current behaviors of STO films deposited at 500 and 550 ± C were controlled by Schottky emission with applied electric field.
We report the dependence of Si–SiO2 interface trap density after Fowler–Nordheim (F/N) stress on various capping materials between gate stacks and an inter layer dielectric (ILD) in a NAND Flash memory cell. The interface trap density was characterized by charge pumping method (CPM). When the capping layer is an oxide, the Nit after F/N stress is approximately 2×1011 cm-2, which is about 50% smaller than that with a nitride layer. We found that the oxide layer causes compressive stress whereas the nitride layer causes a relatively high tensile stress in the underlying substrate by measuring the warp change of the substrate. To correlate the interface state density and data retention characteristics, we measured Vt shift after high-temperature baking. When an oxide capping layer is used, the retention characteristics of memory devices are greatly improved compared to the nitride capping case. These results show a good correlation between the interface characteristics and mechanical stress behaviors.
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