Analysis of Thermal Variation of DRAM Retention Time

Cho, M.; Kim, Y.; Woo, D. S.; Kim, S.; Shim, M.S.; Park, Y.; Lee, W.; Ryu, Byung-Il

doi:10.1109/relphy.2006.251257

Cited by 12 publications

(2 citation statements)

References 7 publications

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“…This means the dominating failure mechanism changes with temperature. Judged from the activation energies, GIDL appears to be the major leakage source for 90nm devices stressed above 75°C [4], and hot carrier degradation [5] dominates below 75°C for all three technologies. Future work may include bit analysis at the test-structure level to reveal the dominating mechanism.…”

Section: Test3mentioning

confidence: 99%

A study of scaling effects on DRAM reliability

White

Qin

Bernstein

2011

2011 Proceedings - Annual Reliability and Maintainability Symposium

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In this study, commercial 512Mb Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) modules from three progressive technologies130nm, 110nm and 90nm -were selected for experimentation to investigate degradation trends as a function of scaling. High temperature, high voltage accelerated stress testing was performed to characterize DRAM reliability and failure rates. Retention time degradation over time as a function of stress was also studied.For each technology generation, two distinct soft error populations were observed: Tail Distribution, characterized by randomly distributed weak bits with Weibull slope =1, and Main Distribution with Weibull slope greater than 1. Retention time was found to degrade exponentially with time. Analysis reveals multiple failure mechanisms are involved in retention time degradation. Activation energy was found to change with stress temperature for all three technologies.There are several observations with regard to scaling effects on DRAM reliability. First, the smaller the technology, the larger the operating current increases in percentage after high temperature, high voltage accelerated stress. Second, cell retention time variation decreases as technology scales down. Third, 90nm DRAM has the largest soft-error failure rate among three technologies under equivalent stress, 110nm DRAM has better reliability performance than 130nm at 55°C and 75°C, and 130nm DRAM is the best at 125°C. Studies continue into the scaling effects on reliability of progressive DRAM technologies.

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Section: Test3mentioning

confidence: 99%

A study of scaling effects on DRAM reliability

White

Qin

Bernstein

2011

2011 Proceedings - Annual Reliability and Maintainability Symposium

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“…Because HBM2 is composed of multiple DRAM dies, it inherits the thermal characteristics of DRAM and the diagnostic limitations owing to the stacked structure [6,7]. The retention issue in DRAM is caused by the leakage current from the storage capacitors inside the memory bit cells, which is generally the most sensitive to temperature [8][9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Temperature Estimation of HBM2 Channels with Tail Distribution of Retention Errors in FPGA-HBM2 Platform

et al. 2022

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High-bandwidth memory 2 (HBM2) vertically stacks multiple dynamic random-access memory (DRAM) dies to achieve a small form factor and high capacity. However, it is difficult to diagnose HBM2 issues owing to their structural complexity and 2.5D integration with heterogeneous chips. The effects of the temperature at the base logic die (TL), and the refresh interval at the stacked DRAM dies, were experimentally investigated by counting the dynamic retention errors in the eight channels in an HBM2. TL was indirectly controlled by the heatsink temperature (TS). The lognormal distribution represents the distribution of the cell counts with varying refresh times. All Z-magnitudes (multiples of the distribution standard deviation) over the various refresh cycle times (RCTs) up to 2.045 s in a single channel at TL of 70 °C appeared below 4.4, which means that the error bits belong to the tail distribution. The Z-differences in the eight channels were distinctively larger than the Z-differences of the same channels at a constant temperature, demonstrating that the temperature difference in the stacked dies resulted in larger Z-differences. The largest Z-difference was 0.091 for all the channels at an RCT of 1.406 s, which was approximately 4.82 times smaller than the Z-difference between the TL temperatures of 70 °C and 80 °C in a single channel. The Z-difference between the TL temperatures of 70 °C and 72 °C in a single channel was approximately the same as the Z-difference in all the channels at an RCT of 2.045 s.

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Wafer to Wafer Hybrid Bonding for DRAM Applications

Park

Lee

et al. 2022

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)

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Analysis of Thermal Variation of DRAM Retention Time

Cited by 12 publications

References 7 publications

A study of scaling effects on DRAM reliability

A study of scaling effects on DRAM reliability

Temperature Estimation of HBM2 Channels with Tail Distribution of Retention Errors in FPGA-HBM2 Platform

Wafer to Wafer Hybrid Bonding for DRAM Applications

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