2012
DOI: 10.1109/tpel.2012.2190425
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DC Offset Error Compensation for Synchronous Reference Frame PLL in Single-Phase Grid-Connected Converters

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Cited by 104 publications
(41 citation statements)
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“…Typically, the measured back-EMF is digitalized through matching circuits including voltage sensor, low pass filter, and A/D converter. As a result, a DC offset error may be generated from the voltage sensor itself because of sensor errors, the thermal variation of the analog electric device and the quantization error of the A/D converter [11][12][13][14].…”
Section: Back-emf-based Sensorless Methodsmentioning
confidence: 99%
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“…Typically, the measured back-EMF is digitalized through matching circuits including voltage sensor, low pass filter, and A/D converter. As a result, a DC offset error may be generated from the voltage sensor itself because of sensor errors, the thermal variation of the analog electric device and the quantization error of the A/D converter [11][12][13][14].…”
Section: Back-emf-based Sensorless Methodsmentioning
confidence: 99%
“…When using the sensorless control method based on the back-EMF estimation, the back-EMF information is measured by the voltage sensor of the system after passing the digital controller signal through a low pass filter (LPF) and analog to digital conversion (ADC). In this process, back-EMF measurement errors can occur due to the nonlinearity of the voltage sensor, the thermal variation of the analog electric device, and ADC quantization errors [11][12][13][14]. At this time, the main component of any occurring nonlinear errors is the direct current (DC) offset error, and when this DC offset error component occurs, it causes a pulsation in the synchronous coordinate system d axis voltage.…”
Section: Introductionmentioning
confidence: 99%
“…It should be mentioned that the developed OSG exhibits DC offset rejection by integrating a simple integral loop. This is different from DC offset elimination loops based on the error between the input signal and the output in-phase signal proposed in [14] and [15]. Subsequently, the new AF-SPLL is proposed.…”
Section: Introductionmentioning
confidence: 99%
“…In [15], the focus is on rejecting the dc offset in the single-phase synchronous reference frame PLL. This algorithm can be implemented by a simple integral operation and the proportional-integral (PI) controller without additional hardware.…”
Section: Introductionmentioning
confidence: 99%