2016
DOI: 10.5370/jeet.2016.11.6.1707
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Improved DC Offset Error Compensation Algorithm in Phase Locked Loop System

Abstract: -This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-lo… Show more

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Cited by 2 publications
(3 citation statements)
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“…Equation (12) is converted into the synchronous coordinate system using Equation (6), and it can be calculated as Equation (13). The d-axis voltage of Equation (12) …”
Section: The Proposed DC Offset Error Compensation Methodsmentioning
confidence: 99%
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“…Equation (12) is converted into the synchronous coordinate system using Equation (6), and it can be calculated as Equation (13). The d-axis voltage of Equation (12) …”
Section: The Proposed DC Offset Error Compensation Methodsmentioning
confidence: 99%
“…Typically, the measured back-EMF is digitalized through matching circuits including voltage sensor, low pass filter, and A/D converter. As a result, a DC offset error may be generated from the voltage sensor itself because of sensor errors, the thermal variation of the analog electric device and the quantization error of the A/D converter [11][12][13][14]. Figure 4 represents the error factors in the voltage measurement path.…”
Section: Effect Of DC Offset Errormentioning
confidence: 99%
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