Data Injection Attack Against Electronic Devices With Locally Weakened Immunity Using a Hardware Trojan

Kaji, Shuichiro; Kinugawa, Masahiro; Fujimoto, Daisuke; Hayashi, Yu-ichi

doi:10.1109/temc.2018.2849105

Cited by 11 publications

(5 citation statements)

References 10 publications

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“…Specific IEMI attacks against UAS include high-altitude electromagnetic pulses (i.e., high-altitude nuclear detonation that produce intense radiated peak field strengths that can damage avionics) [51] [53], jamming (i.e., high-powered electromagnetic signals targeted at avionics) [54] [55] [56], and data/signal injection attacks even at low power levels [57] [58] [49]. Additionally, malicious hardware modifications [59] can amplify avionics' susceptibility to create localized zones of weakened immunity to external RF exploitation; this leads to arbitrary data injection, reading sensor measurements/processor memories, and denial-of-service crashes. A detailed discussion on such attacks and their respective attack vectors are beyond the scope of our study as our focus will be on system-and environmental-related sources of interference.…”

Section: Cyber Securitymentioning

confidence: 99%

UAS-Guided Analysis of Electric and Magnetic Field Distribution in High-Voltage Transmission Lines (Tx) and Multi-Stage Hybrid Machine Learning Models for Battery Drain Estimation

Jim Hassan,

Jangula,

Ramchandra

et al. 2024

IEEE Access

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Unmanned aerial systems/vehicles (UAS/UAVs) are widely employed for inspecting highvoltage (HV) Tx lines, characterized by elevated electric (E) and magnetic (H) fields. Operating on batteries, these UAVs are equipped with various electrical sensors, microprocessors, and motors, all susceptible to E/H field effects. This paper explores the distribution of E/H fields in multiple HVTx lines and a microwave tower. Data was collected from one 250kV DC , four AC Tx lines (69kV, 230kV, 345kV, and 500kV), and one microwave tower, utilizing DJI UAVs (M2EA, M30, and M300) equipped with onboard setups. Measurements included E field in V/m, H field in mG, Battery voltage in V, Battery current in A, Battery percentage, Battery Temperature in F, latitude, and longitude. Preliminary findings highlight larger E/H field levels within AC Tx lines than DC Tx lines. The paper discusses conditions influencing E/H field strength during UAV operation. Additionally, a proposed multi-staged random forest regressor (RFR) and k-nearest neighbor (KNN) hybrid machine learning (ML) model forecasts UAV battery drain. Results indicate that the hybrid RFR and KNN model yields lower MAPE values compared to standalone models. INDEX TERMS Battery, electric field, hybrid model, KNN regressor, machine learning, magnetic field, power drain, random forest regressor, transmission lines, unmanned aerial vehicle.

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Section: Cyber Securitymentioning

confidence: 99%

UAS-Guided Analysis of Electric and Magnetic Field Distribution in High-Voltage Transmission Lines (Tx) and Multi-Stage Hybrid Machine Learning Models for Battery Drain Estimation

Jim Hassan,

Jangula,

Ramchandra

et al. 2024

IEEE Access

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“…Subramani et al [19] demonstrated an HT in a wireless network by exploiting the forward error correction block to create a covert channel. Similarly, Kaji et al [36] proposed a data injection attack by exploiting HT to create specific electromagnetic waves as a covert channel. (iv) Remote activation . Since an attacker may have limited physical access to deployed devices, triggering HTs remotely is an ideal choice.…”

Section: In‐house Design Team Attacksmentioning

confidence: 99%

Ten years of hardware Trojans: a survey from the attacker's perspective

Xue

Liu

et al. 2020

IET Computers & Digital Techniques

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In the last decade, hardware Trojan has emerged as a serious concern in integrated circuit (IC) industry. As such, hardware Trojan detection techniques have been studied extensively. However, in order to develop reliable and effective defenses, it is important to figure out how hardware Trojans are implemented in practical scenarios. In this paper, we attempt to make a review of the hardware Trojan design and implementations in the last decade and also provide an outlook. Unlike all previous surveys that discuss Trojans from the defender's perspective, for the first time, we study the Trojans from the attacker's perspective, focusing on the attacker's methods, capabilities and challenges when he designs and implements a hardware Trojan. Particularly, the following questions are explored. What are the current methods and capabilities of attackers after ten years of research and development? By considering more and more sophisticated hardware Trojan detection techniques, what challenges do the attackers face, and vice versa? First, we present adversarial models in terms of the adversary's methods, adversary's capabilities and adversary's challenges in seven practical hardware Trojan implementation scenarios: in-house design team attacks, third-party intellectual property (3PIP) vendor attacks, computer-aided design (CAD) tools attacks, fabrication stage attacks, testing stage attacks, distribution stage attacks, and field programmable gate array (FPGA) Trojan attacks. Second, we analyze the hardware Trojan implementation methods under each adversarial model in terms of seven aspects/metrics: hardware Trojan attack scenarios, the attacker's motivation, feasibility (the practicality of the attacks), detectability (anti-detection capability of that kind of Trojan), protection and prevention suggestions for the designer, overhead analysis, and case studies of Trojan implementations. Finally, future directions on hardware Trojan attacks and defenses are discussed. This paper also presents several new insights and assumptions for the first time, including considering the Trojans not only from the copyright owner's perspective, but also from the users' perspective, and discussing the hardware Trojan attacks in the testing phase and in the distribution phase. This paper can hopefully provide a reference for future works on building effective hardware Trojan defenses.

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“…As the hardware-level attack, a malicious logic (well-known as hardware Trojan) hidden in internal logic might be premeditatedly designed to cause the program execution failures at key points or could create the backdoors for both confidential information leakages and subsequent system hijacking to attackers [ 5 ]. On the other hand, the external physical attacks can exploit the three invasive methods of bus monitoring, offline analysis, and data tampering to steal the sensitive information and/or activate the built-in hardware Trojan to disorganize the program execution through external access interfaces [ 6 , 7 ]. System-level attacks mainly exploit the security vulnerabilities or bugs in software applications to disturb the instruction executions or cause buffer overflows by injecting malicious codes for subverting the system trustworthiness and obtaining the unauthorized control of system.…”

Section: Introductionmentioning

confidence: 99%

High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems

et al. 2021

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Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and program execution failures for SoCs at key points. Therefore, this paper presents a security SoC architecture with integrating a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator for achieving high-efficiency data processing to guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks. The architecture design has been implemented and verified on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform. Based on evaluation of the cryptographic accelerator in terms of performance overhead, security capability, processing efficiency, and resource consumption, experimental results show that the parallel cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as 2.65% on typical 8-KB I/D-Caches, and its data processing efficiency is around 3 times that of the pipelined AES-GCM construction. The reinforced SoC under the data tampering attacks and benchmark tests confirms the effectiveness against external physical attacks and satisfies a good trade-off between high-efficiency and hardware overhead.

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Data Injection Attack Against Electronic Devices With Locally Weakened Immunity Using a Hardware Trojan

Cited by 11 publications

References 10 publications

UAS-Guided Analysis of Electric and Magnetic Field Distribution in High-Voltage Transmission Lines (Tx) and Multi-Stage Hybrid Machine Learning Models for Battery Drain Estimation

UAS-Guided Analysis of Electric and Magnetic Field Distribution in High-Voltage Transmission Lines (Tx) and Multi-Stage Hybrid Machine Learning Models for Battery Drain Estimation

Ten years of hardware Trojans: a survey from the attacker's perspective

High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems

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