Physical unclonable functions (PUFs), a form of physical security primitive, enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs). Many PUF implementations have been proposed to generate these unique n-bit binary strings. However, they often offer insufficient uniqueness and reliability when implemented on FPGAs and can consume excessive resources. To address these problems, in this article we present an efficient, lightweight, and scalable PUF identification (ID) generator circuit that offers a compact design with good uniqueness and reliability properties and is specifically designed for FPGAs. A novel post-characterisation methodology is also proposed that improves the reliability of a PUF without the need for any additional hardware resources. Moreover, the proposed post-characterisation method can be generally used for any FPGA-based PUF designs. The PUF ID generator consumes 8.95% of the hardware resources of a low-cost Xilinx Spartan-6 LX9 FPGA and 0.81% of a Xilinx Artix-7 FPGA. Experimental results show good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing. In particular, the reliability of the PUF is close to 100% over an environmental temperature range of 25 • C to 70 • C with ±10% variation in the supply voltage. CCS Concepts: • Security and privacy → Tamper-proof and tamper-resistant designs; Hardwarebased security protocols; Embedded systems security;

Glycidyl methacrylate bonded β-cyclodextin (GMA-β-CD) is synthesized as a new chiral monomer by direct chemical bonding with GMA using a fast and a simple alternative procedure. Very, rigid and homogenous monolithic columns were prepared by polymerization of GMA-β-CD monomer with ethylene dimethacrylate (EDMA), in the presence of commonly used porogens and a charged achiral monomer to form a versatile chiral monolith. This is the first report in which a preparation procedure for a methacrylate-bonded CD is introduced for chiral separations in CEC. The degree of substitution (DS) of GMA-β-CD monomer and mobile phase parameters were optimized to achieve highest enantioselectivity and plate number. To evaluate the GMA-β-CD monolithic column, different classes of chiral compounds were screened. Under the optimized β-CD monolith phase and the optimum mobile phase conditions, 30 neutral and basic chiral compounds and two acidic compounds could be separated. The high chemical and mechanical stability, homogenous microflow and no loss of material at the interface allows for the first time the feasibility of applying this polymer-based monolithic column for CEC coupled to ESI-MS. Compared to CEC-UV, CEC-ESI-MS showed higher sensitivity and lower resolution. However, resolution greater than 1.0 can still be obtained for majority of the select tested compound in CEC-ESI-MS with at least three out of seven compound providing Rs≥1.5. The results reinforce the potential of GMA-β-CD monolithic columns for chiral separations with high sensitivity in CEC-ESI-MS. Finally, using hexobarbital as model chiral analyte, the monolithic column demonstrated excellent stability and reproducibility of retention time and enantioselectivity.

The pressure output of a pump cannot be increased simply by connecting several of them in series. This barrier is eliminated with the micropump developed in this work. The pump is actually an assembly of a number of fundamental pump units connected in series. The maximum pressure output of this pump assembly is directly proportional to the number of serially connected pump units. Theoretically, one can always enhance the pressure output by adding more pump units in the assembly, but in reality the upper pressure is constrained by the microtees or microunions joining the pump components. With commercially available microtees and microunions, pressures of more than 1200 bar have been achieved. We have recently experimented using open capillaries to build this pump, but many capillaries have to be utilized in parallel to produce an adequate flow to drive HPLC separations. In this paper, we synthesize polymer monoliths inside 75 μm i.d. capillaries, use these monoliths to assemble miniaturized pumps, characterize the performance of these pumps, and employ these pumps for HPLC separations of intact proteins. By tuning the experimental parameters for monolith preparations, we obtain both negatively and positively charged submicrometer capillary channels conveniently. Each monolith in a 75 μm i.d. capillary is equivalent to several thousands of open capillaries.

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Abstract-Current approaches for building physical unclonable function (PUF) designs resistant to machine learning attacks often suffer from large resource overhead and are typically difficult to implement on field programmable gate arrays (FPGAs). In this paper we propose a new arbiterbased multi-PUF (MPUF) design that utilises a Weak PUF to obfuscate the challenges to a Strong PUF and is harder to model than the conventional arbiter PUF using machine learning attacks. The proposed PUF design shows a greater resistance to attacks, which have been successfully applied to other Arbiter PUFs. A mathematical model is presented to analyse the complexity and obfuscation properties of the proposed PUF design. Moreover, we show that it is feasible to implement the proposed MPUF design on a Xilinx Artix-7 FPGA, and that it achieves a good uniqueness result of 40.60 % and uniformity of 37.03 %, which significantly improves over previous work into multi-PUF designs.

With the rapid development of the Internet of Things (IoT), security has attracted considerable interest. Conventional security solutions that have been proposed for the Internet based on classical cryptography cannot be applied to IoT nodes as they are typically resource-constrained. A physical unclonable function (PUF) is a hardware-based security primitive and can be used to generate a key online or uniquely identify an integrated circuit (IC) by extracting its internal random differences using so-called challenge-response pairs (CRPs). It is regarded as a promising low-cost solution for IoT security. A logic reconfigurable PUF (RPUF) is highly efficient in terms of hardware cost. This article first presents a new classification for RPUFs, namely circuitbased RPUF (C-RPUF) and algorithm-based RPUF (A-RPUF); two Exclusive OR (XOR)-based RPUF circuits (an XOR-based reconfigurable bistable ring PUF (XRBR PUF) and an XOR-based reconfigurable ring oscillator PUF (XRRO PUF)) are proposed. Both the XRBR and XRRO PUFs are implemented on Xilinx Spartan-6 field-programmable gate arrays (FPGAs). The implementation results are compared with previous PUF designs and show good uniqueness and reliability. Compared to conventional PUF designs, the most significant advantage of the proposed designs is that they are highly efficient in terms of hardware cost. Moreover, the XRRO PUF is the most efficient design when compared with previous RPUFs. Also, both the proposed XRRO and XRBR PUFs require only 12.5% of the hardware resources of previous bitstable ring PUFs and reconfigurable RO PUFs, respectively, to generate a 1-bit response. This confirms that the proposed XRBR and XRRO PUFs are very efficient designs with good uniqueness and reliability. CCS Concepts: • Security and privacy → Security in hardware; Embedded systems security; • Hardware → Reconfigurable logic applications;

A PUF is a physical security primitive that allows to extract intrinsic digital identifiers from electronic devices. It is a promising candidate to improve security in lightweight devices targeted at IoT applications due to its low cost nature. The Arbiter PUF or APUF has been widely studied in the technical literature. However it often suffers from disadvantages such as poor uniqueness and reliability, particularly when implemented on FPGAs due to physical layout restrictions. To address these problems, a new design known as FF-APUF has been proposed; it offers a compact architecture, combined with good uniqueness and reliability properties, and is well suited to FPGA implementation. Many PUF designs have been shown to be vulnerable to machine learning (ML) based modelling attacks. In this paper, initial tests show that to attack the FF-APUF design requires more effort for the adversary than a conventional APUF design. A comprehensive analysis of the experimental results for the FF-APUF design is presented to show this outcome. An improved APUF design with a balanced routing, and the proposed FF-APUF design are both implemented on an Xilinx Artix-7 FPGA at 28 nm technology. The empirical min-entropy of the FF-APUF design across different devices is shown to be more than twice that of the conventional APUF design.

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