Crystalline Oxide Semiconductor-based 3D Bank Memory System for Endpoint Artificial Intelligence with Multiple Neural Networks Facilitating Context Switching and Power Gating

Yakubo, Yuto; Furutani, Kazuma; Toyotaka, Kouhei; Katagiri, Haruki; Fujita, Masashi; Kozuma, Munehiro; Ando, Yasuhisa; Kurokawa, Yasuyoshi; Nakura, Toru; Yamazaki, Shunpei

doi:10.1109/isscc42615.2023.10067603

Cited by 4 publications

(2 citation statements)

References 6 publications

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“…2. The planar FET has a shape similar to that of previously reported OSFETs and has been used in various applications [14], [15], [16], [17]. The planar FET includes a bottom gate (BG) electrode and a top gate (TG) electrode; the threshold voltage (Vth) of the planar FET can be controlled by varying the BG voltage [7].…”

Section: Introductionmentioning

confidence: 95%

1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs

Hirose,

Okamoto,

Komura

et al. 2024

IEEE J. Electron Devices Soc.

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We present a three-dimensional (3D) DRAM prototype, which is formed using oxide semiconductor FETs (OSFETs) monolithically stacked on a Si CMOS. The OSFETs are composed of a one-layer planar FET and two-layer vertical FETs (VFETs). The 1T1C memory cells in the VFET layers and a primary sense amplifier in the planar FET layer, which are formed using heterogeneous OSFETs, provide various circuit functions in the DRAM. The operation of the 3D DRAM in a 1-Mbit memory array is demonstrated for the first time. The results show that the proposed DRAM operates with read and write times of 60 ns and 50 ns, respectively. The leakage current of the memory cell is extremely low (comparable to an 2.2  10 -19 A/cell at 85C), indicating that over 99 of the data are retained in the memory array after one hour at 85C without refresh.

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Section: Introductionmentioning

confidence: 95%

1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs

Hirose,

Okamoto,

Komura

et al. 2024

IEEE J. Electron Devices Soc.

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“…They also have low leakage current and high voltage tolerance derived from wide bandgap, good interfaces with high-k dielectric, and high thermal stability. To take advantage of them, there are some researches applying them to not only FPD devices but also large-scale integration (LSI) devices [2]. And recently, they are attracting more attentions for monolithic 3-D integration in back end of line (BEOL) [3], [4], [5], [6], [7], [8] and 3-D structure memory devices [9], [10] [Fig.…”

Section: Introductionmentioning

confidence: 99%

A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel for 3-D Integrated Devices

Hikake,

Li,

Hao

et al. 2024

IEEE Trans. Electron Devices

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We have developed atomic layer deposition (ALD) process of InGaOx (IGO) and InSnOx for transistor channel and electrode and investigated the tradeoff among mobility, electrostatics, and reliability in single-gate (SG) IGO FETs. Threshold voltage (V th ) shift after positive gate bias was observed especially in high Ga concentration and thin IGO channel devices, which can be attributed to excess oxygen. We also extracted interface and bulk state density (D it and N bulk ) using the subthreshold swing (SS) measurement results from the channel thickness dependence. D it is as low as 1-2 × 10 11 cm −2 eV −1 , which means the formation of the defect-less interface between IGO channel and HfO 2 gate dielectric. Ga concentration dependence of N bulk indicates the impact of O 2 dimer generation in high Ga concentration devices. To break the characteristics tradeoff, we fabricated multigate nanosheet (NS) IGO FETs and demonstrated normally OFF operation, high mobility (>30 cm 2 /Vs), and high reliability. The drive current of the double-gate (DG) IGO FET is 2.2 times higher and the mobility is 1.2 times higher than that of the SG IGO FET, thanks to the multichannel structure and excess oxygen reduction by passivation process. The difference in positive bias instability (PBI) and negative bias instability (NBI) degradation between SG and DG structure was discussed by comparing the electric field distribution of TCAD simulation results of SG and DG IGO FET. This work shows the most well-balanced performance among preceding ALD IGO FETs with respect to mobility, V th , and SS, and shows the possibility of future 3-D back end of line (BEOL) monolithic and 3-D memory integration using ALD IGO channel.

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A 3-D Bank Memory System for Low-Power Neural Network Processing Achieved by Instant Context Switching and Extended Power Gating Time

Toyotaka,

Yakubo,

Furutani

et al. 2024

IEEE J. Electron Devices Soc.

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Crystalline Oxide Semiconductor-based 3D Bank Memory System for Endpoint Artificial Intelligence with Multiple Neural Networks Facilitating Context Switching and Power Gating

Cited by 4 publications

References 6 publications

1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs

1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs

A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel for 3-D Integrated Devices

A 3-D Bank Memory System for Low-Power Neural Network Processing Achieved by Instant Context Switching and Extended Power Gating Time

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