Cost reduction and evaluation of a temporary faults detecting technique

Anghel, Lorena; Nicolaidis, M.

doi:10.1109/date.2000.840845

Cited by 100 publications

(42 citation statements)

References 10 publications

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“…The TED technique is first introduced in [14] and is called transient fault detection (TFD). TFD is used to detect timing errors known to be the result of local variations and soft errors due to energetic particles.…”

Section: Originalmentioning

confidence: 99%

Sub-threshold operation of a timing error detection latch

Turnquist¹,

Koskinen²

2009

2009 Ph.D. Research in Microelectronics and Electronics

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Ajoitusvirheentunnistus (TED) mahdollistaa energian kulutuksen vähentämisen mikroprosessoreissa. Tässä diplomityössä on kaksi versiota ajoitusvirheentunnistavasta salvasta (esim. TDTBsubI ja TDTBsubII) ja systeemitason testipiiri (SystemTest), joka käyttää TDTBsub salpaa, mikä on suunniteltu toimimaan kynnysalueen alapuolella. Diplomityö esittelee ensin dynaamisen jännitteen skaalauksen (DVS), koska TED käytetään sellaisissa järjestelmissä. Seuraavaksi esitellään teoriaa kynnysalueen alapuolen suunnittelun haasteista. Sitten esitellään molempien TDTBsub salpojen ja SystemTest-lohkojen suunnittelu. Simulaatiotuloksia esitellään keskittyen operaatiotaajuuteen, energian kulutukseen ja toimintavarmuuteen variaatiot huomioon ottaen. Operoitaessa kynnysalueen alapuolella TDTB-piirillä keskityttiin koon mitoittamiseen ja suunnittelutyyliin. Ennen kaikkea kaikkien komponenttien mitoituksen piti olla suurempi kuin minimi CMOS-tekniikan leveydet. Vaikka mitoittamisella saavutettiin toimintavarmuutta kynnysalueen alapuolella toimittaessa myös energian kulutus kasvoi siellä toimittaessa. Perinteisiä vuotovirtojen vähentäviä mitoitustoimenpiteitä tehtiin suurimmalle osalle komponenteista. Logiikkatyyli on tärkeää kynnysalueen alapuolella operoitaessa. TDTBsubII salvassa uuden tekniikan näytetään antavan systeemitason suorituskykyä. Simulaatioilla näytettiin kuinka ajoitusvirheentunnistus kykeni toimimaan kynnystason alapuolella. TDTBsubI:n ja yhteenlaskun testipiirin piirinkuvio tehtiin 65nm CMOS-prosessilla. TDTBsubII salpaa ei tehty, koska se suunniteltiin piirin määräajan jälkeen. Piiriä tarkasteltaessa osoittautui, että piiri ei toiminut. Piirin toimimattomuus johtui tuotantovaiheessa tapahtuneesta virheestä eikä suunnittelusta. Avainsanat:sub-threshold,weak inversion,low power,low voltage,digital CMOS To operate TDTBsub into sub-threshold, attention was given to sizing and logic style. In general, the sizing of all components was required to be larger than the minimum CMOS width. Although this provided robustness in sub-threshold, the energy consumption in above sub-threshold was much higher. General leakage reduction sizing techniques were also applied to the majority of components. The choice of logic style is important for sub-threshold operation. In the TDTBsubII latch, a new technique is shown to provide system-level capability. Simulations displayed the capability of TED in sub-threshold. The layout of TDTBsubI and an adder test circuit were constructed in 65 nm CMOS. The TDTBsubII latch was not built since it was designed after the chip deadline. Upon inspection of the chip, it was determined to be inoperative. This mistake was a result of the manufacturering process and not the design in this work. Keywords:sub-threshold, weak inversion, low power, low voltage, digital CMOS ii ForewordThe work for this thesis was carried out at the Electronic Circuit Design Laboratory (ECDL) of TKK. The financial support of this project was provided by the Academy of Finland. The project was coordinated with University of Turku ...

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Section: Originalmentioning

confidence: 99%

Sub-threshold operation of a timing error detection latch

Turnquist¹,

Koskinen²

2009

2009 Ph.D. Research in Microelectronics and Electronics

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“…The interested reader will also find clever applications in the work of Kehl [14], Anghel [4], and Uht [24].…”

Section: Btwc Design In Other Application Domainsmentioning

confidence: 99%

Deployment of better than worst-case design: solutions and needs

Austin¹,

Bertacco²

2005 International Conference on Computer Design

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“…Hence, an online error detection and retry procedure was considered better [5]. Online or concurrent error detection can be achieved by using self checking circuits [6], [7] or by exploiting temporal redundancy of signals [5]. Self checking circuits may require high hardware cost for arbitrary logic functions.…”

Section: B Related Workmentioning

confidence: 99%

“…The time domain majority voter presented in [4] has a performance overhead since the sampling is started after the longest path in the circuit settles. Hence, an online error detection and retry procedure was considered better [5]. Online or concurrent error detection can be achieved by using self checking circuits [6], [7] or by exploiting temporal redundancy of signals [5].…”

Section: B Related Workmentioning

confidence: 99%

A highly-efficient technique for reducing soft errors in static CMOS circuits

Krishnamohan

Mahapatra

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.

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Abstract-Soft errors are functional failures resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by high-energy particle strikes or electrical noise. Traditionally, they have been deemed to be a problem in memory structures, for which effective techniques (such as error correcting codes) are well known. However, due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits. Existing circuit and architectural approaches to addressing soft errors in logic circuits have appreciable area/cost, performance, and/or energy overheads or are limited to particular types of circuits (combinational or sequential). We present a very efficient and systematic error masking technique that uses the same circuitry to cope with soft errors in combinational and sequential circuits. It prevents an SET pulse of width less than approximately half of the slack available in the propagation path from latching and turning into a soft error. The SET is masked without additional delay and within the clock cycle time in an area-and energy-efficient manner, which makes this technique attractive for commodity as well as reliabilitycritical applications. Our technique also tolerates soft errors in the overhead circuitry, which we minimize through clustering. Application of our technique to ISCAS85 benchmark circuits yields an average SER reduction of 70.93% with an average area overhead of only 11.98%.

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Cost reduction and evaluation of a temporary faults detecting technique

Cited by 100 publications

References 10 publications

Sub-threshold operation of a timing error detection latch

Sub-threshold operation of a timing error detection latch

Deployment of better than worst-case design: solutions and needs

A highly-efficient technique for reducing soft errors in static CMOS circuits

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