Deployment of better than worst-case design: solutions and needs

Austin, Todd; Bertacco, Valeria

doi:10.1109/iccd.2005.43

Cited by 20 publications

(10 citation statements)

References 26 publications

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“…To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. tion and reliability of the circuit [11,12,13]. In addition, such technique is also very helpful for post-silicon debug as we are able to find the root cause of the timing errors easily.…”

Section: Introductionmentioning

confidence: 99%

Re-synthesis for cost-efficient circuit-level timing speculation

Liu

Yuan

2011

Proceedings of the 48th Design Automation Conference

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Section: Introductionmentioning

confidence: 99%

Re-synthesis for cost-efficient circuit-level timing speculation

Liu

Yuan

2011

Proceedings of the 48th Design Automation Conference

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“…Numerous techniques at all design stages are available to catch soft errors before they manifest in the output response or in the state of a circuit: error correcting codes [2] have been proposed, redundancy in time [3] or space [4] is applied, circuit structures are widened and thereby hardened during layout [5], [6]. But when implementing these techniques in a design, bugs may be introduced.…”

Section: Introductionmentioning

confidence: 99%

Robustness Check for Multiple Faults Using Formal Techniques

Frehse

Fey

Suflow

et al. 2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

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Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft errors can be taken on all design stages, e.g. the architectural level, algorithmic level, or on the layout level. Whether the final implementation contains flaws or really provides robustness to soft errors remains to be checked.Here, we propose an approach to formally verify the robustness of a circuit with respect to multiple soft errors. We propose a fault model that prunes the exponentially sized space of multiple soft errors and an algorithm that automatically analyzes a given circuit.

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“…Conventional design methodology requires designers to embed a large design guardband to prevent any timing failure. This conservative design methodology, however, inevitably diminishes the benefit of technology scaling [4]. Consequently, there is a growing research interest to achieve online timing error resilience.…”

Section: Introductionmentioning

confidence: 99%

InTimeFix

Yuan

2013

Proceedings of the 50th Annual Design Automation Conference

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With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and adverse aging effects. In most cases, these reliability threats manifest themselves as timing errors on critical speed-paths of the circuit, if a large design guard band is not reserved. This work presents a novel insitu timing error masking technique, namely InTimeFix, by introducing fine-grained redundant approximation circuit into the design to provide more timing slack for speed-paths. The synthesis of the redundant circuit relies on simple structural analysis of the original circuit, which is easily scalable to large IC designs. Experimental results show that InTimeFix significantly increases circuit timing slack with low area/power cost.

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Deployment of better than worst-case design: solutions and needs

Abstract: Abstract

Cited by 20 publications

References 26 publications

Re-synthesis for cost-efficient circuit-level timing speculation

Re-synthesis for cost-efficient circuit-level timing speculation

Robustness Check for Multiple Faults Using Formal Techniques

InTimeFix

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